| 2: 1 Multiplexer Using Different Design Styles: Comparative Analysis T Dua, A Rajput STM J. Adv. Robot 7, 5-13, 2020 | 7 | 2020 |
| Novel CMOS and PTL based half subtractor designs A Rajput, T Dua, R Kumawat, A Srinivasulu 2021 IEEE International Symposium on Smart Electronic Systems (iSES), 165-168, 2021 | 5 | 2021 |
| Half Adder using Dif-ferent Design Styles: A Review on Comarative Study A Rajput, T Dua, R Kumawat, A Srinivasulu Jornal of Advancements in Robotics 7 (3), 26-32, 2020 | 5 | 2020 |
| An efficient novel latch design for sequential applications T Dua, KG Sharma, T Sharma International Conference on Recent Advances and Innovations in Engineering …, 2014 | 2 | 2014 |
| High-speed set D flip-flop design for portable applications T Dua, VK Barodiya, V Arya, N Choudhary Proceedings of Integrated Intelligence Enable Networks and Computing: IIENC …, 2021 | 1 | 2021 |
| Novel Two-Bit Magnitude Comparators for IOT Applications A Rajput, T Dua, S Gour, R Kumawat International Conference on Emerging Trends in Expert Applications …, 2023 | | 2023 |
| Area Efficient and Low Power Half Subtractor Using Transmission Gate CMOS Logic T Dua, A Rajput, A Srinivasulu, R Kumawat 2022 IEEE Region 10 Symposium (TENSYMP), 1-6, 2022 | | 2022 |
| Novel 8: 1 Multiplexer for Low Power and Area Efficient Design in Industry 4.0 T Dua, A Rajput, S Gour Industry 4.0, AI, and Data Science, 13-39, 2021 | | 2021 |
| 2 Novelfor 8: 1 Multiplexerand T Dua, A Rajput, S Gour Industry 4.0, AI, and Data Science: Research Trends and Challenges, 13, 2021 | | 2021 |
| FDP on EMERGING TRENDS IN ORGANIC ELECTRONICS J Neeraj, P Rahul, R Pallav Electronics and Communication, 2020 | | 2020 |
| Area Efficient Level Sensitive Flip-Flops–A Performance Comparison T Dua, KG Sharma, T Sharma | | |
