Prof. (Dr.) Usha Sandeep Mehta
Prof. (Dr.) Usha Sandeep Mehta
Professor, EC, Institute of Technology, Nirma University, Ahmedabad
Verified email at - Homepage
Cited by
Cited by
Hamming Distance Based Reordering and Columnwise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based Codes
US Mehla, KS Dasgupta, NM Devashrayee
VLSI Design, 2010. VLSID'10. 23rd International Conference on, 33-38, 2010
Modified selective Huffman coding for optimization of test data compression, test application time and area overhead
US Mehta, KS Dasgupta, NM Devashrayee
Journal of Electronic Testing 26 (6), 679-688, 2010
Run-length-based test data compression techniques: how far from entropy and power bounds?—a survey
US Mehta, KS Dasgupta, NM Devashrayee
VLSI Design 2010, 2010
A survey of radiation hardening by design (rhbd) techniques for electronic systems for space application
R Trivedi, US Mehta
International Journal of Electronics and Communication Engineering …, 2016
Hamming distance based 2-D reordering with power efficient don't care bit filling: optimizing the test data compression method
US Mehta, NM Devashrayee, KS Dasgupta
2010 International Symposium on System on Chip, 1-7, 2010
A Simple and Efficient Procedure for Synthesis of Biologically Active 1, 2, 4-Triazolo-[3, 4-b]-1, 3, 4-thiadiazole-2-arylthiazolidine-4-one Derivatives
K Parmar, S Parajapati, R Patel, R Patel
Res. J. Chem. Sci 1 (1), 18-24, 2011
Survey of test data compression technique emphasizing code based schemes
US Mehta, KS Dasgupta, NM Devashrayee
2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009
Defect characterization and testing of QCA devices and circuits: A survey
V Dhare, U Mehta
2015 19th International Symposium on VLSI Design and Test, 1-2, 2015
A simple synthesis process for combinational QCA circuits: QSynthesizer
V Dhare, U Mehta
2019 32nd international conference on VLSI design and 2019 18th …, 2019
Fault analysis of QCA combinational circuit at layout & logic level
V Dhare, U Mehta
2015 IEEE International WIE Conference on Electrical and Computer …, 2015
Development of Radiation Hardened by Design (RHBD) primitive gates using 0.18 μm CMOS technology
R Trivedi, NM Devashrayee, US Mehta, NM Desai, H Patel
2015 19th International Symposium on VLSI Design and Test, 1-2, 2015
Analysis of don’t care bit filling techniques for optimization of compression and scan power
KA Bhavsar, US Mehta
International Journal of Computer Applications 18 (3), 0975-8887, 2011
Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method.
US Mehta, KS Dasgupta, NM Devashrayee
VLSI Design 2011, 756561:1-756561:8, 2011
Transition probabilistic approach for detection and diagnosis of Hardware Trojan in combinational circuits
J Popat, U Mehta
2016 IEEE Annual India Conference (INDICON), 1-6, 2016
Design and implementation of FPGA Based G code compatible CNC lathe controller
MA Saifee, US Mehta
Technology 7 (1), 75-86, 2016
Suitability of various low-power testing techniques for IP core-based SoC: a survey
U Mehta, K Dasgupta, N Devashrayee
VLSI Design 2011, 2011
Frequency dependant bit appending: an enhancement to statistical codes for test data compression
US Mehta, KS Dasgupta, NM Devashrayee
2009 Annual IEEE India Conference, 1-4, 2009
Multiple missing cell defect modeling for QCA devices
VH Dhare, US Mehta
Journal of Electronic Testing 34 (6), 623-641, 2018
Quantum-dot Cellular Automata (QCA): A Survey
U Mehta, V Dhare
arXiv preprint arXiv:1711.08153, 2017
A statistical test data compression technique with adaptive bit filling and AI based reordering: optimization for compression and scan power
H Parmar, U Mehta, EC Branch
International journal of VLSI and signal processing application 1, 15-24, 2011
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