Hamming Distance Based Reordering and Columnwise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based Codes US Mehla, KS Dasgupta, NM Devashrayee VLSI Design, 2010. VLSID'10. 23rd International Conference on, 33-38, 2010 | 37 | 2010 |
Run-length-based test data compression techniques: how far from entropy and power bounds?--a survey US Mehta, KS Dasgupta, NM Devashrayee VLSI Design 2010, 2010 | 33 | 2010 |
Defect characterization and testing of QCA devices and circuits: A survey V Dhare, U Mehta 2015 19th International Symposium on VLSI Design and Test, 1-2, 2015 | 22 | 2015 |
A survey of radiation hardening by design (rhbd) techniques for electronic systems for space application R Trivedi, US Mehta International Journal of Electronics and Communication Engineering …, 2016 | 21 | 2016 |
Quantum-dot cellular automata (QCA): a survey U Mehta, V Dhare arXiv preprint arXiv:1711.08153, 2017 | 20 | 2017 |
Modified selective Huffman coding for optimization of test data compression, test application time and area overhead US Mehta, KS Dasgupta, NM Devashrayee Journal of Electronic Testing 26, 679-688, 2010 | 18 | 2010 |
Survey of test data compression technique emphasizing code based schemes US Mehta, KS Dasgupta, NM Devashrayee 2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009 | 17 | 2009 |
Hamming distance based 2-D reordering with power efficient don't care bit filling: optimizing the test data compression method US Mehta, NM Devashrayee, KS Dasgupta 2010 International Symposium on System on Chip, 1-7, 2010 | 15 | 2010 |
Transition probabilistic approach for detection and diagnosis of Hardware Trojan in combinational circuits J Popat, U Mehta 2016 IEEE Annual India Conference (INDICON), 1-6, 2016 | 11 | 2016 |
Suitability of various low-power testing techniques for IP core-based SoC: a survey U Mehta, K Dasgupta, N Devashrayee VLSI Design 2011, 1-7, 2011 | 10 | 2011 |
A simple synthesis process for combinational QCA circuits: QSynthesizer V Dhare, U Mehta 2019 32nd international conference on VLSI design and 2019 18th …, 2019 | 9 | 2019 |
Multiple missing cell defect modeling for QCA devices VH Dhare, US Mehta Journal of Electronic Testing 34, 623-641, 2018 | 8 | 2018 |
Development of basic fault model and corresponding ATPG for single input missing cell deposition defects in majority voter of QCA V Dhare, U Mehta 2016 IEEE Region 10 Conference (TENCON), 2354-2359, 2016 | 8 | 2016 |
Development of Radiation Hardened by Design (RHBD) primitive gates using 0.18 μm CMOS technology R Trivedi, NM Devashrayee, US Mehta, NM Desai, H Patel 2015 19th International Symposium on VLSI Design and Test, 1-2, 2015 | 8 | 2015 |
Weighted transition based reordering, columnwise bit filling, and difference vector: a power-aware test data compression method U Mehta, KS Dasgupta, NM Devashrayee VLSI Design 2011, 9-9, 2011 | 8 | 2011 |
Uvm based verification of read and write transactions in axi4-lite protocol H Sangani, U Mehta 2022 IEEE region 10 symposium (TENSYMP), 1-5, 2022 | 7 | 2022 |
Design and implementation of FPGA Based G code compatible CNC lathe controller MA Saifee, US Mehta Technology 7 (1), 75-86, 2016 | 7 | 2016 |
Fault analysis of QCA combinational circuit at layout & logic level V Dhare, U Mehta 2015 IEEE International WIE Conference on Electrical and Computer …, 2015 | 7 | 2015 |
Design and implementation of 2-axis circular interpolation controller in field programmable gate array (FPGA) for computer numerical control (CNC) machines and robotics MA Saifee, US Mehta International Journal of Computer Applications 106 (13), 2014 | 7 | 2014 |
Analysis of don’t care bit filling techniques for optimization of compression and scan power KA Bhavsar, US Mehta International Journal of Computer Applications 18 (3), 0975-8887, 2011 | 6 | 2011 |