Jandhyala Srivatsava
Jandhyala Srivatsava
Semiconductor Industry, Bangalore
Verified email at iiit.ac.in
Title
Cited by
Cited by
Year
BSIM—SPICE models enable FinFET and UTB IC designs
N Paydavosi, S Venugopalan, YS Chauhan, JP Duarte, S Jandhyala, ...
IEEE Access 1, 201-215, 2013
1142013
BSIM compact MOSFET models for SPICE simulation
YS Chauhan, S Venugopalan, N Paydavosi, P Kushwaha, S Jandhyala, ...
Proceedings of the 20th International Conference Mixed Design of Integrated …, 2013
222013
A simple charge model for symmetric double-gate MOSFETs adapted to gate-oxide-thickness asymmetry
S Jandhyala, R Kashyap, C Anghel, S Mahapatra
IEEE Transactions on Electron Devices 59 (4), 1002-1007, 2012
202012
An efficient robust algorithm for the surface-potential calculation of independent DG MOSFET
S Jandhyala, S Mahapatra
IEEE Transactions on Electron Devices 58 (6), 1663-1671, 2011
192011
Inclusion of body doping in compact models for fully-depleted common double gate MOSFET adapted to gate-oxide thickness asymmetry
S Jandhyala, S Mahapatra
Electronics Letters 48 (13), 794-795, 2012
152012
An accurate all CMOS temperature sensor for IoT applications
SK Maddikatla, S Jandhyala
2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 349-354, 2016
92016
BSIM-IMG with Improved Surface Potential Calculation Recipe
P Kushwaha, C Yadav, H Agarwal, J Srivatsava, S Khandelwal, JP Duarte, ...
IEEE India Conference (INDICON), 2014, 2014
72014
Process variability analysis in DSM through statistical simulations and its implications to design methodologies
RSTG Srinivasa, J Srivatsava
9th International Symposium on Quality Electronic Design (isqed 2008), 325-329, 2008
72008
based stochastic neuron for Boltzmann machine to solve “maximum cut” problem
D Khilwani, V Moghe, S Lashkare, V Saraswat, P Kumbhare, ...
APL Materials 7 (9), 091112, 2019
62019
An accurate all CMOS bandgap reference voltage with integrated temperature sensor for IoT applications
SK Maddikatla, S Jandhyala
2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 524-528, 2016
52016
Piecewise linearization technique for compact charge modeling of independent DG MOSFET
S Jandhyala, A Abraham, C Anghel, S Mahapatra
IEEE Transactions on Electron Devices 59 (7), 1974-1979, 2012
52012
Accuracy-configurable approximate multiplier with error detection and correction
A Mehta, S Maurya, N Sharief, BM Pranay, S Jandhyala, S Purini
TENCON 2015-2015 IEEE Region 10 Conference, 1-4, 2015
42015
Accuracy Configurable Modified Booth Multiplier Using Approximate Adders
SJ BM Pranay
2015 IEEE International Symposium on Nanoelectronic and Information Systems …, 2015
42015
Improvements in efficiency of surface potential computation for independent DG MOSFET
A Abraham, S Jandhyala, S Mahapatra
IEEE Transactions on Electron Devices 59 (4), 1199-1202, 2012
42012
Visual Inertial Odometry At the Edge: A Hardware-Software Co-design Approach for Ultra-low Latency and Power
DK Mandal, S Jandhyala, OJ Omer, GS Kalsi, B George, G Neela, ...
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 960-963, 2019
32019
A 1.3 V–1.8 V configurable phase locked loop with an adaptive charge pump
S Jandhyala, S Tapse
2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics …, 2016
32016
A power efficient phase frequency detector and low mismatch charge pump in on-chip clock generator
S Jandhyala, S Tapse
2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics …, 2016
32016
Quasi-Static Terminal-Charge Model for Symmetric Double-Gate Ferroelectric FETs
H Mulaka, S Jandhyala
IEEE TRANSACTIONS ON ELECTRON DEVICES 63 (3), 940-945, 2016
32016
Architecture to generate binary descriptor for image feature point
G Neela, DK Mandal, GS Kalsi, P Laddha, OJ Omer, A Thyagharajan, ...
US Patent App. 16/449,896, 2019
2019
Simulation Study of III-V Lateral Tunnel FETs with Gate-Drain Underlap
VAR Yempada, S Jandhyala
International Symposium on VLSI Design and Test, 716-726, 2019
2019
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Articles 1–20