| Condition assessment of power transformers based on multi‐attributes using fuzzy logic C Ranga, AK Chandel, R Chandel IET Science, Measurement & Technology 11 (8), 983-990, 2017 | 43 | 2017 |
| A novel unified model for copper and MLGNR interconnects using voltage-and current-mode signaling schemes Y Agrawal, MG Kumar, R Chandel IEEE transactions on electromagnetic compatibility 59 (1), 217-227, 2016 | 39 | 2016 |
| A new approach to design low power CMOS flash A/D converter SS Chauhan, S Manabala, SC Bose, R Chandel International Journal of VLSI design & Communication Systems (VLSICS) 2 (2), 100, 2011 | 39 | 2011 |
| Comprehensive model for high-speed current-mode signaling in next generation MWCNT bundle interconnect using FDTD technique Y Agrawal, MG Kumar, R Chandel IEEE Transactions on Nanotechnology 15 (4), 590-598, 2016 | 38 | 2016 |
| Power system dynamic state estimation using prediction based evolutionary technique V Basetti, AK Chandel, R Chandel Energy 107, 29-47, 2016 | 33 | 2016 |
| Repeater insertion in global interconnects in VLSI circuits R Chandel, S Sarkar, RP Agarwal Microelectronics international 22 (1), 43-50, 2005 | 30 | 2005 |
| An efficient crosstalk model for coupled multiwalled carbon nanotube interconnects MG Kumar, R Chandel, Y Agrawal IEEE Transactions on Electromagnetic Compatibility 60 (2), 487-496, 2017 | 29 | 2017 |
| Classification of power quality problems using wavelet based artificial neural network AK Chandel, G Guleria, R Chandel 2008 IEEE/PES Transmission and Distribution Conference and Exposition, 1-5, 2008 | 27 | 2008 |
| Carbon nanotube interconnects− a promising solution for VLSI circuits MG Kumar, Y Agrawal, R Chandel IETE Journal of Education 57 (2), 46-64, 2016 | 26 | 2016 |
| An analysis of interconnect delay minimization by low-voltage repeater insertion R Chandel, S Sarkar, RP Agarwal Microelectronics journal 38 (4-5), 649-655, 2007 | 26 | 2007 |
| Modelling and performance analysis of dielectric inserted side contact multilayer graphene nanoribbon interconnects GK Mekala, Y Agrawal, R Chandel IET Circuits, Devices & Systems 11 (3), 232-240, 2017 | 25 | 2017 |
| Analysis of low power high performance XOR gate using GDI technique AK Nishad, R Chandel 2011 International Conference on Computational Intelligence and …, 2011 | 25 | 2011 |
| Crosstalk Analysis of Current-Mode Signalling-Coupled RLC Interconnects Using FDTD Technique Y Agrawal, R Chandel IETE Technical Review 33 (2), 148-159, 2016 | 24 | 2016 |
| Design of a low power flip-flop using CMOS deep sub micron technology S Naik, R Chandel 2010 International Conference on Recent Trends in Information …, 2010 | 20 | 2010 |
| Comparative study of ant colony and genetic algorithms for VLSI circuit partitioning SS Gill, R Chandel, A Chandel International Journal of Electrical and Computer Engineering 4 (6), 00-00, 2009 | 19 | 2009 |
| Expert system for condition monitoring of power transformer using fuzzy logic C Ranga, AK Chandel, R Chandel Journal of Renewable and Sustainable Energy 9 (4), 044901, 2017 | 17 | 2017 |
| High-performance current mode receiver design for on-chip VLSI interconnects Y Agrawal, R Chandel, R Dhiman Intelligent Computing and Applications: Proceedings of the International …, 2015 | 16 | 2015 |
| Delay and power management of voltage-scaled repeater driven long interconnects R Chandel, S Sarkar, RP Agarwal International Journal of Modelling and Simulation 27 (4), 333-339, 2007 | 16 | 2007 |
| Compact models and performance investigations for subthreshold interconnects R Dhiman, R Chandel Springer India, 2015 | 15 | 2015 |
| Design and analysis of a modified low power CMOS full adder using gate-diffusion input technique KK Chaddha, R Chandel Journal of low power electronics 6 (4), 482-490, 2010 | 14 | 2010 |
Dr. Yash AgrawalAssistant Prof, Dhirubhai Ambani Institute of Information and Communication Technology (DA-IICT)Verified email at nith.ac.in
