| Battery-driven system design: A new frontier in low power design K Lahiri, A Raghunathan, S Dey, D Panigrahi Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design …, 2002 | 538 | 2002 |
| Battery life estimation of mobile embedded systems D Panigrahi, C Chiasserini, S Dey, R Rao, A Raghunathan, K Lahiri VLSI Design 2001. Fourteenth International Conference on VLSI Design, 57-63, 2001 | 279 | 2001 |
| System-level performance analysis for designing on-chip communication architectures K Lahiri, A Raghunathan, S Dey IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2001 | 266 | 2001 |
| LOTTERYBUS: A new high-performance communication architecture for system-on-chip designs K Lahiri, A Raghunathan, G Lakshminarayana Proceedings of the 38th annual design automation conference, 15-20, 2001 | 192 | 2001 |
| Evaluation of the traffic-performance characteristics of system-on-chip communication architectures K Lahiri, A Raghunathan, S Dey VLSI Design 2001. Fourteenth International Conference on VLSI Design, 29-35, 2001 | 178 | 2001 |
| Battery discharge characteristics of wireless sensor nodes: An experimental analysis C Park, K Lahiri, A Raghunathan 2005 Second Annual IEEE Communications Society Conference on Sensor and Ad …, 2005 | 170 | 2005 |
| Design space exploration for optimizing on-chip communication architectures K Lahiri, A Raghunathan, S Dey IEEE transactions on computer-aided design of integrated circuits and …, 2004 | 170 | 2004 |
| Efficient exploration of the SoC communication architecture design space K Lahiri, A Raghunathan, S Dey IEEE/ACM International Conference on Computer Aided Design. ICCAD-2000. IEEE …, 2000 | 151 | 2000 |
| The LOTTERYBUS on-chip communication architecture K Lahiri, A Raghunathan, G Lakshminarayana IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14 (6), 596-608, 2006 | 120 | 2006 |
| Power analysis of mobile 3D graphics B Mochocki, K Lahiri, S Cadambi Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 102 | 2006 |
| Power analysis of system-level on-chip communication architectures K Lahiri, A Raghunathan Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware …, 2004 | 98 | 2004 |
| Power monitors: A framework for system-level power estimation using heterogeneous power models N Bansal, K Lahiri, A Raghunathan, ST Chakradhar 18th International Conference on VLSI Design held jointly with 4th …, 2005 | 83 | 2005 |
| Signature-based workload estimation for mobile 3D graphics BC Mochocki, K Lahiri, S Cadambi, XS Hu Proceedings of the 43rd annual design automation conference, 592-597, 2006 | 73 | 2006 |
| Fast performance analysis of bus-based system-on-chip communication architectures K Lahiri, A Raghunathan, S Dey 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1999 | 68 | 1999 |
| Performance analysis of systems with multi-channel communication architectures K Lahiri, A Raghunathan, S Dey VLSI Design 2000. Wireless and Digital Imaging in the Millennium …, 2000 | 65 | 2000 |
| Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips K Lahiri, A Raghunathan, G Lakshminarayana, S Dey Proceedings of the 37th Annual Design Automation Conference, 513-518, 2000 | 64 | 2000 |
| Dynamically configurable bus topologies for high-performance on-chip communication K Sekar, K Lahiri, A Raghunathan, S Dey IEEE transactions on very large scale integration (VLSI) systems 16 (10 …, 2008 | 49 | 2008 |
| Design of high-performance system-on-chips using communication architecture tuners K Lahiri, A Raghunathan, G Lakshminarayana, S Dey IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004 | 49 | 2004 |
| FLEXBUS: A high-performance system-on-chip communication architecture with a dynamically configurable topology K Sekar, K Lahiri, A Raghunathan, S Dey Proceedings of the 42nd annual Design Automation Conference, 571-574, 2005 | 45 | 2005 |
| High performance communication architecture for circuit designs using probabilistic allocation of resources K Lahiri, A Raghunathan, G Lakshminrayana US Patent 6,877,053, 2005 | 41 | 2005 |
Anand RaghunathanProfessor of Electrical and Computer Engineering, Purdue UniversityVerified email at purdue.edu
