Minsoo Rhu
Title
Cited by
Cited by
Year
Scnn: An accelerator for compressed-sparse convolutional neural networks
A Parashar, M Rhu, A Mukkara, A Puglielli, R Venkatesan, B Khailany, ...
ACM SIGARCH Computer Architecture News 45 (2), 27-40, 2017
4712017
vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design
M Rhu, N Gimelshein, J Clemons, A Zulfiqar, SW Keckler
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
1812016
A locality-aware memory hierarchy for energy-efficient GPU architectures
M Rhu, M Sullivan, J Leng, M Erez
2013 46th Annual IEEE/ACM International Symposium on Microarchitecture …, 2013
1102013
Priority-based cache allocation in throughput processors
D Li, M Rhu, DR Johnson, M O'Connor, M Erez, D Burger, DS Fussell, ...
2015 IEEE 21st International Symposium on High Performance Computer …, 2015
842015
CAPRI: prediction of compaction-adequacy for handling control-divergence in GPGPU architectures
M Rhu, M Erez
ACM SIGARCH Computer Architecture News 40 (3), 61-71, 2012
682012
Compressing DMA engine: Leveraging activation sparsity for training deep neural networks
M Rhu, M O'Connor, N Chatterjee, J Pool, Y Kwon, SW Keckler
2018 IEEE International Symposium on High Performance Computer Architecture …, 2018
662018
The dual-path execution model for efficient GPU control flow
M Rhu, M Erez
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
592013
Maximizing SIMD resource utilization in GPGPUs with SIMD lane permutation
M Rhu, M Erez
Proceedings of the 40th Annual International Symposium on Computer …, 2013
502013
Architecting an energy-efficient DRAM system for GPUs
N Chatterjee, M O’Connor, D Lee, DR Johnson, SW Keckler, M Rhu, ...
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
492017
GPUVolt: Modeling and characterizing voltage noise in GPU architectures
J Leng, Y Zu, M Rhu, M Gupta, VJ Reddi
Proceedings of the 2014 international symposium on Low power electronics and …, 2014
322014
Optimization of arithmetic coding for JPEG2000
M Rhu, IC Park
IEEE Transactions on Circuits and systems for Video Technology 20 (3), 446-451, 2009
242009
Virtualizing deep neural networks for memory-efficient neural network design
M Rhu, N Gimelshein, J Clemons, A Zulfiqar, SW Keckler
arXiv preprint arXiv:1602.08124 43, 2016
232016
Beyond the memory wall: A case for memory-centric hpc system for deep learning
Y Kwon, M Rhu
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
192018
Clean-ecc: High reliability ecc for adaptive granularity memory system
SL Gong, M Rhu, J Kim, J Chung, M Erez
Proceedings of the 48th International Symposium on Microarchitecture, 611-622, 2015
192015
Tensordimm: A practical near-memory processing architecture for embeddings and tensor operations in deep learning
Y Kwon, Y Lee, M Rhu
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
152019
A novel trace-pipelined binary arithmetic coder architecture for JPEG2000
M Rhu, IC Park
2009 IEEE Workshop on Signal Processing Systems, 243-248, 2009
102009
A case for memory-centric HPC system architecture for training deep neural networks
Y Kwon, M Rhu
IEEE Computer Architecture Letters 17 (2), 134-138, 2018
82018
System, method, and computer program product for prioritized access for multithreaded processing
DR Johnson, M Rhu, JM O'Connor, SW Keckler
US Patent App. 14/147,395, 2015
82015
Structurally sparsified backward propagation for faster long short-term memory training
M Zhu, J Clemons, J Pool, M Rhu, SW Keckler, Y Xie
arXiv preprint arXiv:1806.00512, 2018
72018
Prema: A predictive multi-task scheduling algorithm for preemptible neural processing units
Y Choi, M Rhu
2020 IEEE International Symposium on High Performance Computer Architecture …, 2020
62020
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