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Dr. Amit Jain
Dr. Amit Jain
Verified email at cmrit.ac.in
Title
Cited by
Cited by
Year
A new SPICE macro model of single electron transistor for efficient simulation of single-electronics circuits
A Jain, A Ghosh, NB Singh, SK Sarkar
Analog Integrated Circuits and Signal Processing 82, 653-662, 2015
212015
A modified macro model approach for SPICE based simulation of single electron transistor
A Ghosh, A Jain, NB Singh, SK Sarkar
Journal of Computational electronics 15, 400-406, 2016
192016
Stability and reliability analysis of hybrid CMOS-SET circuits—a new approach
A Jain, A Ghosh, NB Singh, SK Sarkar
Journal of Computational and Theoretical Nanoscience 11 (12), 2519-2525, 2014
162014
Design and implementation of SET-CMOS hybrid half subtractor
A Ghosh, A Jain, NB Singh, SK Sarkar
2014 Annual IEEE India Conference (INDICON), 1-4, 2014
132014
A new compact analytical model of single electron transistor for hybrid SET–MOS circuits
A Jain, BS Nameriakpam, SK Sarkar
Solid-State Electronics 104, 90-95, 2015
112015
Small-signal model for the single-electron transistor: part I
A Ghosh, A Jain, S Gharami, SK Sarkar
Journal of Computational electronics 16, 296-306, 2017
72017
Stability aspects of single electron threshold logic based 4 bit carry look ahead adder
A Ghosh, A Jain, NB Singh, SK Sarkar
Proceedings of the 2015 third international conference on computer …, 2015
72015
Design and simulation of single electron threshold logic gate based programmable logic array
A Ghosh, A Jain, SK Sarkar
Procedia technology 10, 866-874, 2013
72013
Design and simulation of nanoelectronic data transfer system with an emphasis on reliability and stability analysis
A Ghosh, A Jain, SK Sarkar
Analog Integrated Circuits and Signal Processing, 2019
62019
Design and reliability analysis of a 4: 1 MUX using single electron tunneling technology based threshold logic gate
A Jain, SK Sarkar
Journal of electron devices 15, 1241-1248, 2012
62012
Millimeter-wave analog pre-distorted power amplifier at 65nm node
NA Quadir, S Kashfi, A Jain, L Albasha
2019 International Conference on Communications, Signal Processing, and …, 2019
52019
Single electron threshold logic based Feynman gate implementation
A Ghosh, A Jain, NB Singh, SK Sarkar
2016 Second international conference on research in computational …, 2016
52016
Reliability aspects and performance analysis of single electron threshold logic based programmable logic array
A Ghosh, A Jain, N Basanta Singh, SK Sarkar
Journal of Computational and Theoretical Nanoscience 12 (9), 2405-2414, 2015
52015
Lean-SE: framework combining lean thinking with the SDLC process
M Deshmukh, A Jain
Ubiquitous Intelligent Systems: Proceedings of ICUIS 2021, 127-133, 2022
42022
A 0.5 V LNA Design for 2.4 GHz Wireless Body Area Network Applications
V Reddy, P Sammeta, R Kumari, NA Quadir, A Jain
2019 3rd International conference on Electronics, Communication and …, 2019
42019
Analytical modeling of read noise margin of a CNFET based 6T SRAM cell
P Saha, A Jain, SK Sarkar
Analog Integrated Circuits and Signal Processing 83, 369-376, 2015
42015
Integrating Drain Gating and Lector Techniques for Leakage Power Reduction in Ultra Deep Submicron Technology
T Harikrishna, S Kumar, A Jain
2021 5th International Conference on Trends in Electronics and Informatics …, 2021
32021
Analysis of Control Strategies of Leakage Power Considering Decoder Optimization
S Saha, AK Jain
Solid State Technology 63 (5), 427-436, 2020
32020
An Ultra Low Power Low noise Operational Transconductance Amplifier for Biomedical Front-end Applications
N Chaya, A Ghosh, B Srinivas, A Jain
2020 International Conference on Inventive Computation Technologies (ICICT …, 2020
32020
A wide-band, low-power grounded active inductor with high Q factor for RF applications
L Bharath, D Anila, CN Ajay, B Shravani, A Jain
International Conference on Communication, Computing and Electronics Systems …, 2020
32020
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