| Comparative Analysis of STT and SOT based MRAMs for Last Level Caches R SAHA, YP PUNDIR, PK PAL Journal of Magnetism and Magnetic Materials, 2022 | 19 | 2022 |
| Effect of gate length on performance of 5nm node N-channel nano-sheet transistors for analog circuits YP Pundir, R Saha, PK Pal Semiconductor Science and Technology 36 (1), 015010, 2020 | 15 | 2020 |
| Effect of Temperature on Performance of 5-nm Node Silicon Nanosheet Transistors for Analog Applications YP PUNDIR, A BISHT, R SAHA, PK PAL Silicon, 2022 | 8 | 2022 |
| Air-spacers as analog-performance booster for 5 nm-node N-channel nanosheet transistor YP Pundir, A Bisht, R Saha, PK Pal Semiconductor Science and Technology, 2021 | 8 | 2021 |
| Design of an area and energy-efficient last-level cache memory using STT-MRAM R Saha, YP Pundir, PK Pal Journal of Magnetism and Magnetic Materials 529, 167882, 2021 | 8 | 2021 |
| Mixed-mode circuit simulations with 5 nm Node Nanosheet Transistors using TCAD YP Pundir, R Saha, PK Pal 2020 International Conference on Advances in Computing, Communication …, 2020 | 3 | 2020 |
| Impact of size, latency of cache-L1 and workload over system performance R Saha, YP Pundir, S Yadav, PK Pal 2020 International Conference on Advances in Computing, Communication …, 2020 | 2 | 2020 |
| Microcontroller based data acquisition system using error reduction technique D Biswas, K Kumar, V Rohilla, GS Kathait, P Thapliyal, AS Bahuguna, ... International Journal of Engineering, Science and Technology 11 (3), 40-48, 2019 | 2 | 2019 |
| Performance analysis of nanosheet transistor with drain/source extension and high-k spacer optimizations for analog applications A Bisht, YP Pundir, PK Pal Analog Integrated Circuits and Signal Processing 116 (1-2), 35-47, 2023 | 1 | 2023 |
| Effect of process-induced variations on analog performance of silicon based nanosheet transistor YP Pundir, A Bisht, R Saha, PK Pal Silicon 15 (10), 4449-4455, 2023 | 1 | 2023 |
| Power supply variations and analog performance of 5-nm node silicon Nanosheet transistor YP Pundir, A Bisht, R Saha, AS Bahuguna, K Kumar, PK Pal 2022 International Conference on Advances in Computing, Communication and …, 2022 | 1 | 2022 |
| Electro-Thermal analysis of vertically stacked gate all around nano-sheet transistor A Bisht, YP Pundir, PK Pal international symposium on VLSI design and test, 126-136, 2022 | 1 | 2022 |
| Object Motion estimation using edge detection and background subtraction with block matching algorithm. S Thapliyal, YP Pundir, AS Bahuguna, S Semwal RICE, 345-348, 2017 | 1 | 2017 |
| Nanosheet Transistor with Inter-bridge Channels for Superior Delay Performance: A Comparative Study A Bisht, YP Pundir, PK Pal Silicon 15 (12), 5175-5185, 2023 | | 2023 |
| Performance Analysis of Nanosheet Transistors for Analog Applications YP Pundir National Institute of Technology Uttarakhand, 2022 | | 2022 |
| Design of U-Shaped Slot Quad Band Patch Antenna K Kumar, AS Bahuguna, YP Pundir, D Biswas | | 2022 |
| A Review of Various Digital Modulation Schemes Used in Wireless Communications AS Bahuguna, K Kumar, YP Pundir, Alaknanda, V Bijalwan Proceedings of Integrated Intelligence Enable Networks and Computing: IIENC …, 2021 | | 2021 |
| Design and Development of DVH-H Transmitter and Receiver YP Pundir, SK Gupta Indian Institute of Science Bangalore, 2007 | | 2007 |
| FPGA based Design of Reed Solomon Decoder for DVB-H Receiver YP Pundir | | |
Pankaj Kumar PalAssistant Professor, Department of Electronics Engineering, NIT UttarakhandVerified email at nituk.ac.in
