| Physical scaling limits of FinFET structure: A simulation study G Saini, AK Rana International Journal of VLSI design & communication Systems (VLSICS) 2 (1 …, 2011 | 50 | 2011 |
| New low-power techniques: leakage feedback with stack & sleep stack with keeper PK Pal, RS Rathore, AK Rana, G Saini 2010 International Conference on Computer and Communication Technology …, 2010 | 32 | 2010 |
| A graded channel dual-material gate junctionless mosfet for analog applications V Pathak, G Saini Procedia Computer Science 125, 825-831, 2018 | 29 | 2018 |
| Asymmetric dual-k spacer trigate FinFET for enhanced analog/RF performance G Saini, S Choudhary Journal of Computational Electronics 15, 84-93, 2016 | 16 | 2016 |
| A stable and power efficient SRAM cell G Saini 2015 International Conference on Computer, Communication and Control (IC4), 1-5, 2015 | 16 | 2015 |
| Leakage behavior of underlap FinFET structure: A simulation study G Saini, AK Rana, PK Pal, S Jadav 2010 International Conference on Computer and Communication Technology …, 2010 | 16 | 2010 |
| Efficient power management circuit for RF energy harvesting with 74.27% efficiency at 623nW available power G Saini, S Sarkar, M Arrawatia, MS Baghini 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 1-4, 2016 | 15 | 2016 |
| Improving the performance of SRAMs using asymmetric junctionless accumulation mode (JAM) FinFETs G Saini, S Choudhary Microelectronics journal 58, 1-8, 2016 | 14 | 2016 |
| Improving the subthreshold performance of junctionless transistor using spacer engineering G Saini, S Choudhary Microelectronics Journal 59, 55-58, 2017 | 13 | 2017 |
| Impact of radial compression on the conductance of carbon nanotube field effect transistors S Choudhary, G Saini, S Qureshi Modern physics letters B 28 (02), 1450007, 2014 | 13 | 2014 |
| Modeling of dual material surrounding split gate junctionless transistor as biosensor M Maji, G Saini Superlattices and Microstructures 135, 106290, 2019 | 12 | 2019 |
| Improving the performance of dual-k spacer underlap Double Gate TFET A Chauhan, G Saini, PK Yerur Superlattices and microstructures 124, 79-91, 2018 | 10 | 2018 |
| Low power high throughput current mode signalling technique for global VLSI interconnect S Jadav, G Khanna, A Kumar, G Saini 2010 International Conference on Computer and Communication Technology …, 2010 | 10 | 2010 |
| L-shaped tunnelling field effect transistor with hetero-gate dielectric and hetero dielectric box S Beniwal, G Saini 2019 3rd International Conference on Trends in Electronics and Informatics …, 2019 | 9 | 2019 |
| Investigation of trigate JLT with dual-k sidewall spacers for enhanced analog/RF FOMs G Saini, S Choudhary Journal of Computational Electronics 15 (3), 865-873, 2016 | 9 | 2016 |
| Stacked keeper with body bias: A new approach to reduce leakage power for low power VLSI design KN Bhargav, A Suresh, G Saini 2014 IEEE international conference on advanced communications, control and …, 2014 | 8 | 2014 |
| Impact of Gate Length and Doping Variation on the DC and Analog/RF Performance of sub - 3nm Stacked Si Gate-All-Around Nanosheet FET N Yadav, S Jadav, G Saini Silicon 15 (1), 217-228, 2023 | 5 | 2023 |
| Analog/RF performance of source-side only dual-k sidewall spacer trigate junctionless transistor with parametric variations G Saini, S Choudhary Superlattices and Microstructures 100, 757-766, 2016 | 5 | 2016 |
| Effect of random dopant fluctuation in nanoscale junctionless FinFET using low and high-k spacers S Dwivedi, G Saini 2017 8th International Conference on Computing, Communication and Networking …, 2017 | 4 | 2017 |
| Study of self-heating effects on fully depleted SOI MOSFETs with BOX layer engineering SK Pandey, G Saini 2017 International Conference on Trends in Electronics and Informatics (ICEI …, 2017 | 4 | 2017 |
Sudhanshu ChoudharyFaculty at University of North Dakota, USAVerified email at und.edu
