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Ganesh C. Patil
Ganesh C. Patil
Associate Prof. VNIT Nagpur
Verified email at cvn.vnit.ac.in - Homepage
Title
Cited by
Cited by
Year
Review on performance analysis of P3HT: PCBM-based bulk heterojunction organic solar cells
IC Ghosekar, GC Patil
Semiconductor Science and Technology 36 (4), 045005, 2021
442021
A novel δ-doped partially insulated dopant-segregated Schottky barrier SOI MOSFET for analog/RF applications
GC Patil, S Qureshi
Semiconductor science and technology 26 (8), 085002, 2011
342011
Engineering spacers in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS logic circuits
GC Patil, S Qureshi
Semiconductor Science and Technology 27 (4), 045004, 2012
262012
Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits
GC Patil, S Qureshi
Microelectronics Journal 43 (5), 321-328, 2012
252012
Dielectric-modulated bulk-planar junctionless field-effect transistor for biosensing applications
D Singh, GC Patil
IEEE Transactions on Electron Devices 68 (7), 3545-3551, 2021
202021
Performance analysis of feedback field-effect transistor-based biosensor
D Singh, GC Patil
IEEE Sensors Journal 20 (22), 13269-13276, 2020
182020
Impact of concentration variation and thermal annealing on performance of multilayer OSC consisting of sandwiched P3HT layer between PEDOT: PSS and P3HT: PCBM
IC Ghosekar, GC Patil
Microelectronic Engineering 221, 111195, 2020
162020
Asymmetric drain underlap dopant-segregated Schottky barrier ultrathin-body SOI MOSFET for low-power mixed-signal circuits
GC Patil, S Qureshi
Semiconductor science and technology 28 (4), 045002, 2013
132013
Performance analysis and thermal reliability study of multilayer organic solar cells
IC Ghosekar, GC Patil
IEEE Transactions on Device and Materials Reliability 19 (3), 572-580, 2019
92019
Scalability and RF performance of nanoscale dopant segregated Schottky barrier SOI MOSFET
GC Patil, S Qureshi
TENCON 2010-2010 IEEE Region 10 Conference, 1921-1926, 2010
92010
Si3N4:HfO2 dual‐k spacer bulk planar junctionless transistor for mixed signal integrated circuits
R Garike, GC Patil
IET Circuits, Devices & Systems 13 (1), 45-50, 2019
72019
Novel δ-doped partially insulated junctionless transistor for mixed signal integrated circuits
GC Patil, VH Bonge, MM Malode, RG Jain
Superlattices and Microstructures 90, 247-256, 2016
72016
Impact of segregation layer on scalability and Analog/RF performance of Nanoscale Schottky barrier SOI MOSFET
GC Patil, S Qureshi
Journal of Semiconductor Technology and Science 12 (1), 66-74, 2012
72012
Improving organic solar cell efficiency using solution processed poly (3‐hexylthiophene) buffer layer
IC Ghosekar, GC Patil
Micro & Nano Letters 14 (1), 74-77, 2019
62019
Analytical model for 4H-SiC superjunction drift layer with anisotropic properties for ultrahigh-voltage applications
A Naugarhiya, P Wakhradkar, PN Kondekar, GC Patil, RM Patrikar
Journal of Computational Electronics 16, 190-201, 2017
62017
Underlap channel silicon-on-insulator quantum dot floating-gate MOSFET for low-power memory applications
CT Dabhi, GC Patil
Journal of Computational Electronics 15 (4), 1563-1569, 2016
62016
A simple analytical model of 4H-SiC MOSFET for high temperature circuit simulations
GC Patil, SC Wagaj, PM Ghate
2014 Annual IEEE India Conference (INDICON), 1-5, 2014
62014
Asymmetric drain underlap schottky barrier SOI MOSFET for low-power high performance nanoscale CMOS circuits
GC Patil, S Qureshi
2011 IEEE Computer Society Annual Symposium on VLSI, 43-48, 2011
62011
A novel partially insulated Schottky source/drain MOSFET: short channel and self heating effects
GC Patil, S Qureshi
2010 International Conference on Microelectronics, 252-255, 2010
62010
Fabrication and characterization of lead sulfide and multi-walled carbon nanotube based field effect transistors using low cost chemical route
GC Patil, ST Ingle, BR Sankapal
Engineering Research Express 3 (2), 025016, 2021
42021
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