Schuyler Eldridge
Schuyler Eldridge
Senior Staff Compiler Engineer at SiFive
Verified email at sifive.com - Homepage
Title
Cited by
Cited by
Year
Neural network-based accelerators for transcendental function approximation
S Eldridge, F Raudies, D Zou, A Joshi
Proceedings of the 24th edition of the great lakes symposium on VLSI, 169-174, 2014
252014
Towards General-Purpose Neural Network Computing
S Eldridge, J Appavoo, A Joshi, A Waterland, M Seltzer
Proceedings of the 2015 International Conference on Parallel Architecture …, 2015
232015
Resilient low voltage accelerators for high energy efficiency
N Chandramoorthy, K Swaminathan, M Cochet, A Paidimarri, S Eldridge, ...
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
182019
DyHard-DNN: Even more DNN acceleration with dynamic hardware reconfiguration
M Putic, S Venkataramani, S Eldridge, A Buyuktosunoglu, P Bose, M Stan
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
122018
Digest generation
V Gopal, JD Guilford, S Eldridge, GM Wolrich, E Ozturk, WK Feghali
US Patent 9,292,548, 2016
122016
Learning to navigate in a virtual world using optic flow and stereo disparity signals
F Raudies, S Eldridge, A Joshi, M Versace
Artificial Life and Robotics 19 (2), 157-169, 2014
92014
Very low voltage (VLV) design
R Bertran, P Bose, D Brooks, J Burns, A Buyuktosunoglu, ...
2017 IEEE International Conference on Computer Design (ICCD), 601-604, 2017
72017
Phmon: a programmable hardware monitor and its security use cases
L Delshadtehrani, S Canakci, B Zhou, S Eldridge, A Joshi, M Egele
29th {USENIX} Security Symposium ({USENIX} Security 20), 807-824, 2020
62020
Nile: A Programmable Monitoring Coprocessor
L Delshadtehrani, S Eldridge, S Canakci, M Egele, A Joshi
IEEE Computer Architecture Letters, 2017
62017
Chiffre: A Configurable Hardware Fault Injection Framework for RISC-V Systems
S Eldridge, A Buyuktosunoglu, P Bose
Second Workshop on Computer Architecture Research with RISC-V, 2018
32018
A Low Voltage RISC-V Heterogeneous System
S Eldridge, K Swaminathan, N Chandramoorthy, A Buyuktosunoglu, ...
First Workshop on Computer Architecture Research with RISC-V (CARRV 2017), 2017
32017
Determination and correction of physical circuit event related errors of a hardware design
P Bose, A Buyuktosunoglu, S Eldridge, KV Swaminathan, Y Zu
US Patent 10,365,327, 2019
22019
Neural Network Computing Using On-Chip Accelerators
S Eldridge
Boston University, 2016
22016
Exploiting hidden layer modular redundancy for fault-tolerance in neural network accelerators
SEA Joshi
12015
Determination and correction of physical circuit event related errors of a hardware design
P Bose, A Buyuktosunoglu, S Eldridge, KV Swaminathan, Y Zu
US Patent App. 16/874,059, 2020
2020
Low-overhead error prediction and preemption in deep neural network using apriori network statistics
S Venkataramani, S Eldridge, KV Swaminathan, A Buyuktosunoglu, ...
US Patent App. 16/262,832, 2020
2020
Determination and correction of physical circuit event related errors of a hardware design
P Bose, A Buyuktosunoglu, S Eldridge, KV Swaminathan, Y Zu
US Patent 10,690,723, 2020
2020
Self-evaluating array of memory
A Buyuktosunoglu, S Venkataramani, R Joshi, KV Swaminathan, ...
US Patent App. 16/774,505, 2020
2020
Self-evaluating array of memory
A Buyuktosunoglu, S Venkataramani, R Joshi, KV Swaminathan, ...
US Patent 10,607,715, 2020
2020
System and method for consensus-based representation and error checking for neural networks
P Bose, A Buyuktosunoglu, S Eldridge, KV Swaminathan, ...
US Patent App. 15/825,660, 2019
2019
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