| Design and FPGA implementation of lattice wave fractional order digital differentiator A Sharma, TK Rawat Microelectronics Journal 88, 67-78, 2019 | 13 | 2019 |
| FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase A Sharma International Journal of Computer Applications 116 (17), 2015 | 6 | 2015 |
| Implementation of single precision conventional and fused floating point add-sub unit using Verilog A Sharma, S Singh, A Sharma 2017 International Conference on Wireless Communications, Signal Processing …, 2017 | 5 | 2017 |
| Optimum Design and FPGA Implementation of Fractional Order Digital Integrator A Sharma, TK Rawat 2019 6th International Conference on Signal Processing and Integrated …, 2019 | 4 | 2019 |
| FPGA Implementation of Lattice-Wave Half-Order Digital Integrator using Radix- Digit Recoding A Sharma, M Gupta, T Rawat 2022 6th International Conference on Electronics, Communication and …, 2022 | 3 | 2022 |
| Design and FPGA implementation of lattice wave digital notch filter with minimal transient duration A Sharma, TK Rawat, A Agrawal IET Signal Processing 14 (7), 440-447, 2020 | 3 | 2020 |
| Truncated Wallace Based Single Precision Floating Point Multiplier A Sharma, TK Rawat 2018 7th International Conference on Reliability, Infocom Technologies and …, 2018 | 3 | 2018 |
| Implementation of Ex-OR gate using QCA with NNI logic A Bharti, A Sharma 2017 International Conference on Wireless Communications, Signal Processing …, 2017 | 3 | 2017 |
| HaarCascade and LBPH Algorithms in Face Recognition Analysis M Gupta, K Bisht, A Sharma, D Upadhyay 2023 World Conference on Communication & Computing (WCONF), 1-4, 2023 | 2 | 2023 |
| Optimal Design of Fractional-Order Digital Integrator using Lattice Wave Structure A Sharma, M Gupta, T Rawat 2022 8th International Conference on Signal Processing and Communication …, 2022 | 2 | 2022 |
| Triple Notch Filter using Non-Uniform Transmission Lines for UWB Applications M Gupta, A Sharma, DK Upadhyay 2022 6th International Conference On Computing, Communication, Control And …, 2022 | 2 | 2022 |
| Implementation of Adder Circuit Using Quantum-Dot Cellular Automata-Based Logic Gates P Kumari, A Sharma, A Singh Intelligent Communication, Control and Devices, 173-185, 2018 | 2 | 2018 |
| FPGA Implementation of High Speed Multiplier with Optimized Reduction Phase A Singh, A Sharma, P Kumari Intelligent Communication, Control and Devices, 187-195, 2018 | 2 | 2018 |
| Comparative Analysis of Discrete and Fused Floating Point Arithmetic Units and its Application for Fused Butterfly Unit P Purohit, M Gupta, A Sharma International Journal for Advance Research and Development 2 (7), 31-39, 2017 | 1 | 2017 |
| Efficient and Robust Digital Notch Filter Implementation Employing Wave Digital Structure A Sharma, M Gupta Applications of Computational Intelligence Techniques in Communications, 31-41, 2024 | | 2024 |
| Multilingual Obnoxious Message Classification using Bidirectional Encoder Representation from Transformers (BERT) N Banka, S Narang, M Gupta, A Sharma, D Upadhyay 2023 International Conference on Computer, Electronics & Electrical …, 2023 | | 2023 |
| Design and Implementation of Time Varying pole Radius IIR Notch filter with improved performance S Rathore, TK Rawat 2020 2nd International Conference on Advances in Computing, Communication …, 2020 | | 2020 |
| Notch/Peak filter Design and its FPGA Implementation through Wave Digital Structure A Sharma 2020 International Conference on Radar, Antenna, Microwave, Electronics, and …, 2020 | | 2020 |
| Efficient Modeling and Simulation of Signal Processing Systems A Sharma, TK Rawat Advanced Numerical Simulation in Science and Engineering, 32-43, 2020 | | 2020 |
| Efficient and Robust Digital Notch Filter Implementation Employing Wave Digital Structure | | |
