| Tejas: A java based versatile micro-architectural simulator SR Sarangi, R Kalayappan, P Kallurkar, S Goel, E Peter 2015 25th International Workshop on Power and Timing Modeling, Optimization …, 2015 | 56 | 2015 |
| A survey of cache simulators H Brais, R Kalayappan, PR Panda ACM Computing Surveys (CSUR) 53 (1), 1-32, 2020 | 24 | 2020 |
| ParTejas: A parallel simulator for multicore processors G Malhotra, R Kalayappan, S Goel, P Aggarwal, A Sagar, SR Sarangi ACM Transactions on Modeling and Computer Simulation (TOMACS) 27 (3), 1-24, 2017 | 22 | 2017 |
| A survey of checker architectures R Kalayappan, SR Sarangi ACM Computing Surveys (CSUR) 45 (4), 1-34, 2013 | 18 | 2013 |
| A hardware implementation of the MCAS synchronization primitive S Patel, R Kalayappan, I Mahajan, SR Sarangi Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 13 | 2017 |
| SecCheck: A trustworthy system with untrusted components R Kalayappan, SR Sarangi 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 379-384, 2016 | 8 | 2016 |
| Tejas simulator: Validation against hardware SR Sarangi, R Kalayappan, P Kallurkar, S Goel arXiv preprint arXiv:1501.07420, 2015 | 7 | 2015 |
| FluidCheck: A redundant threading-based approach for reliable execution in manycore processors R Kalayappan, SR Sarangi ACM Transactions on Architecture and Code Optimization (TACO) 12 (4), 1-26, 2015 | 4 | 2015 |
| Secx: A framework for collecting runtime statistics for socs with multiple accelerators R Kalayappan, SR Sarangi 2015 IEEE Computer Society Annual Symposium on VLSI, 137-142, 2015 | 4 | 2015 |
| ChunkedTejas: A chunking-based approach to parallelizing a trace-driven architectural simulator R Kalayappan, A Chhabra, SR Sarangi ACM Transactions on Modeling and Computer Simulation (TOMACS) 30 (3), 1-21, 2020 | 3 | 2020 |
| Providing accountability in heterogeneous systems-on-chip R Kalayappan, SR Sarangi ACM Transactions on Embedded Computing Systems (TECS) 17 (5), 1-24, 2018 | 2 | 2018 |
| Surveillance using non‐stealthy sensors: A new intruder model A Bagchi, R Kalayappan, S Sankhla Security and Communication Networks 7 (11), 1900-1911, 2014 | 2 | 2014 |
| On Decomposing Complex Test Cases for Efficient Post-silicon Validation C Harshitha, S Harikrishna, P Rohith, S Chandran, R Kalayappan 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 256-261, 2024 | | 2024 |
| Dynamic Ineffectuality-based Clustered Architectures R Kalayappan, S Chandran arXiv preprint arXiv:2304.12762, 2023 | | 2023 |
| SANNA: Secure Acceleration of Neural Network Applications A Poptani, A Mittal, R Saiya, R Kalayappan, S Chandran 2023 36th International Conference on VLSI Design and 2023 22nd …, 2023 | | 2023 |
| A Formal Approach to Accountability in Heterogeneous Systems-on-Chip R Kalayappan, SR Sarangi IEEE Transactions on Dependable and Secure Computing 18 (6), 2926-2940, 2020 | | 2020 |
