| Apparatus and method for providing hardware security P Chou, L Kothari, LJ Madar III US Patent 8,826,039, 2014 | 42 | 2014 |
| Systems and methods for distributing an aging burden among processor cores P Penzes, M Fullerton, J Hwisung, J Walley, T Sippel, L Kothari US Patent 9,407,272, 2016 | 35 | 2016 |
| Method and system for securely protecting a semiconductor chip without compromising test and debug capabilities L Kothari, P Chou, J Markey US Patent 8,644,499, 2014 | 31 | 2014 |
| Apparatus and method for partitioning, sandboxing and protecting external memories P Chou, L Kothari, LJ Madar III, RS Setty, D Singh US Patent App. 12/714,367, 2011 | 28 | 2011 |
| Protecting external volatile memories using low latency encryption/decryption L Kothari, LJ Madar III US Patent 8,745,411, 2014 | 24 | 2014 |
| Method and system for securely programming OTP memory J Markey, L Kothari, P Chou US Patent 8,918,575, 2014 | 18 | 2014 |
| Architecture of a self-checkpointing microprocessor that incorporates nanomagnetic devices L Kothari, NP Carter IEEE Transactions on Computers 56 (2), 161-173, 2007 | 18 | 2007 |
| Methods of on-chip memory partitioning and secure access violation checking in a system-on-chip L Kothari US Patent 8,745,724, 2014 | 14 | 2014 |
| Electronics device capable of efficient communication between components with asyncronous clocks L Kothari, M Fullerton, R Rajan, V Alarcon US Patent 9,225,343, 2015 | 12 | 2015 |
| Integrated circuit with an adaptable contact pad reconfiguring architecture L Kothari, J Bennett, Z Zhang US Patent 8,744,368, 2014 | 9 | 2014 |
| Protecting data on integrated circuit A Guettaf, L Kothari US Patent 8,074,132, 2011 | 8 | 2011 |
| Apparatus and method for providing hardware security P Chou, L Kothari, LJ Madar III US Patent 9,355,280, 2016 | 6 | 2016 |
| Scalable and configurable system on a chip interrupt controller L Kothari, M Fullerton US Patent 8,782,314, 2014 | 6 | 2014 |
| Clock signal multiplication to reduce noise coupled onto a transmission communication signal of a communications device L Kothari, A Hukkoo, KA Thompson US Patent 8,954,017, 2015 | 5 | 2015 |
| Clock domain crossing serial interface, direct latching, and response codes V Alarcon, W Nabhane, MN Fullerton, L Kothari, RS Patel, CT Hsieh, ... US Patent 8,996,736, 2015 | 2 | 2015 |
| Integrated circuit allowing to test a power management unit based on or more conditions and configuring the plurality of pins to operate in normal and test mode V Alarcon, L Kothari, A Guettaf, K Thompson US Patent 8,856,559, 2014 | 2 | 2014 |
| Apparatus and method to combine pin functionality in an integrated circuit P Penzes, L Kothari, A Hukkoo, M Fullerton, V Alarcon, Z Zhang, ... US Patent App. 13/250,677, 2013 | 2 | 2013 |
| Hall-effect circuits and architectures for nonvolatile system design NP Carter, S Ferrera, L Kothari, S Ye Proceedings of the 2005 European Conference on Circuit Theory and Design …, 2005 | 2 | 2005 |
| Integrated circuit for preventing chip swapping and/or device cloning in a host device L Kothari, P Chou US Patent 8,650,633, 2014 | 1 | 2014 |
| Method and system for hardware enforced virtualization in an integrated circuit J Markey, L Kothari, P Chou US Patent 8,732,806, 2014 | | 2014 |
