| Analytical modeling of channel potential and threshold voltage of double-gate junctionless FETs with a vertical Gaussian-like doping profile B Singh, D Gola, K Singh, E Goel, S Kumar, S Jit IEEE Transactions on Electron Devices 63 (6), 2299-2305, 2016 | 74 | 2016 |
| Dielectric pocket double gate junctionless FET: a new MOS structure with improved subthreshold characteristics for low power VLSI applications B Singh, D Gola, E Goel, S Kumar, K Singh, S Jit Journal of Computational Electronics 15 (2), 502-507, 2016 | 39 | 2016 |
| 2-D analytical threshold voltage model for dielectric pocket double-gate junctionless FETs by considering source/drain depletion effect B Singh, D Gola, K Singh, E Goel, S Kumar, S Jit IEEE Transactions on Electron Devices 64 (3), 901-908, 2017 | 38 | 2017 |
| Subthreshold modeling of tri-gate junctionless transistors with variable channel edges and substrate bias effects D Gola, B Singh, PK Tiwari IEEE Transactions on Electron Devices 65 (5), 1663-1671, 2018 | 31 | 2018 |
| A threshold voltage model of tri-gate junctionless field-effect transistors including substrate bias effects D Gola, B Singh, PK Tiwari IEEE Transactions on Electron Devices 64 (9), 3534-3540, 2017 | 27 | 2017 |
| Analytical modeling of subthreshold characteristics of ion-implanted symmetric double gate junctionless field effect transistors B Singh, D Gola, K Singh, E Goel, S Kumar, S Jit Materials science in semiconductor processing 58, 82-88, 2017 | 26 | 2017 |
| Static and quasi-static drain current modeling of tri-gate junctionless transistor with substrate bias-induced effects D Gola, B Singh, J Singh, S Jit, PK Tiwari IEEE Transactions on Electron Devices 66 (7), 2876-2883, 2019 | 25 | 2019 |
| Ferro-electric stacked gate oxide heterojunction electro-statically doped source/drain double-gate tunnel field effect transistors: A superior structure B Singh, TN Rai, D Gola, K Singh, E Goel, S Kumar, PK Tiwari, S Jit Materials Science in Semiconductor Processing 71, 161-165, 2017 | 19 | 2017 |
| Subthreshold Characteristic Analysis and Models for Tri-Gate SOI MOSFETs Using Substrate Bias Induced Effects D Gola, B Singh, PK Tiwari IEEE Transactions on Nanotechnology 18, 329-335, 2019 | 17 | 2019 |
| Thermal noise models for trigate junctionless transistors including substrate bias effects D Gola, B Singh, P Srinivas, PK Tiwari IEEE Transactions on Electron Devices 67 (1), 263-269, 2019 | 7 | 2019 |
| Subthreshold modeling of graded channel double gate junctionless FETs YS Duksh, B Singh, D Gola, PK Tiwari, S Jit Silicon 13 (4), 1231-1238, 2021 | 6 | 2021 |
| An analytical subthreshold current model of short-channel symmetrical double gate-all-around (DGAA) field-effect-transistors S Bhushan, A Kumar, D Gola, PK Tiwari 2017 Devices for Integrated Circuit (DevIC), 211-215, 2017 | 6 | 2017 |
| Temperature sensitivity analysis of double gate junctionless field effect transistor with vertical Gaussian doping profile B Singh, D Gola, K Singh, E Goel, S Kumar, S Jit 2016 International Conference on Micro-Electronics and Telecommunication …, 2016 | 5 | 2016 |
| AnalyticalModeling of Channel Potential and Threshold Voltage of Double GateJunctionless Field Effect Transistor with a Vertical Gaussian-Like Doping Profile B Singh, D Gola, K Singh, E Goel, S Kumar, S Jit IEEE Transactions on Electron Devices 63 (6), 2299-2305, 2016 | 5 | 2016 |
| Self-heating and negative differential conductance improvement by substrate bias voltage in tri-gate junctionless transistor D Gola, YS Duksh, B Singh, PK Tiwari Silicon 14 (5), 2219-2224, 2022 | 3 | 2022 |
| Performance evaluation of double gate junctionless field effect transistor with vertical Gaussian doping profile B Singh, D Gola, S Kumar, K Singh, E Goel, S Jit 2016 IEEE International Conference on Recent Trends in Electronics …, 2016 | 2 | 2016 |
| Subthreshold Performance Analysis of Double-Fin Multi-channel Junctionless Transistor with Substrate Bias Effects B Singh, D Gola, S Jit TENCON 2019-2019 IEEE Region 10 Conference (TENCON), 1834-1837, 2019 | 1 | 2019 |
| Analytical modeling of analog/RF parameters for trigate junctionless field effect transistor incorporating substrate biasing effects D Gola, B Singh, PK Tiwari TENCON 2019-2019 IEEE Region 10 Conference (TENCON), 1838-1841, 2019 | 1 | 2019 |
| Modeling and Simulation of Trigate Junctionless Field Effect Transistors with Substrate Bias Effects D Gola IIT Patna, 2020 | | 2020 |
| Investigation of Thermal Noise in Trigate Junctionless Transistor D Gola, B Singh, PK Tiwari 2019 International Conference on Electrical, Electronics and Computer …, 2019 | | 2019 |
