Achieveing reduced area by multi-bit flip flop design G Prakash, K Sathishkumar, B Sakthibharathi, S Saravanan, R Vijaysai 2013 International Conference on Computer Communication and Informatics, 1-4, 2013 | 31 | 2013 |
Design and analysis of high speed shift register using Single clock pulse method A Rajaram, P Premalatha, R Sowmiya, S Saravanan, R Vijaysai 2013 International Conference on Computer Communication and Informatics, 1-4, 2013 | 16 | 2013 |
Design and analysis of low power memory built in self test architecture for SoC based design S Vennelakanti, S Saravanan Indian Journal of Science and Technology 8 (14), 1, 2015 | 12 | 2015 |
Design and analysis of scan power reduction based on linear feedback shift register reseeding G Sowmiya, P Premalatha, A Rajaram, S Saravanan, RV Sai 2013 IEEE Conference on Information & Communication Technologies, 638-641, 2013 | 10 | 2013 |
Low power estimation on test compression technique for SoC based design PR Gopal, S Saravanan Indian Journal of Science and Technology 8 (14), 1, 2015 | 9 | 2015 |
Improved CAPTCHA based authentication for E-mail ID K Naveen, S Saravanan, M Lavanya, V Vaithayanathan Indian Journal of Science and Technology 8 (35), 1-4, 2015 | 5 | 2015 |
Recent trends on Post-Silicon validation and debug: An overview R Agalya, S Saravanan 2017 International Conference on Networks & Advances in Computational …, 2017 | 4 | 2017 |
An enhanced load balancing scheduling approach on private clouds M Lavanya, A Ravi, A Aditya, R Samyuktha, V Vaithiyanathan, ... Indian Journal of Science and Technology 8 (35), 1-4, 2015 | 4 | 2015 |
Implementation of a novel data scrambling based security measure in memories for VLSI circuits RV Sai, S Saravanan, V Anandkumar Indian Journal of Science and Technology 8 (35), 1-6, 2015 | 4 | 2015 |
Higher test pattern compression for scan based test vectors using weighted bit position method S Saravanan, R Upadhyay, V Sai ARPN Journal of Engineering and Applied Sciences 7 (3), 256-9, 2012 | 4 | 2012 |
Efficient test sequence generator for area optimization in LFSR reseeding DN Joice, S Saravanan Ind J Sci Technol 9, 29, 2016 | 3 | 2016 |
A constraint-based decentralized task routing approach to large-scale scheduling in cloud environment M Lavanya, TN Janani, S Sushmita, M Sunandha, V Vaithiyanathan, ... Indian J Sci Technol 8 (35), 1-4, 2015 | 3 | 2015 |
Rectifying Various Scan-based Attacks on Secure IC'S C Ramya, S Saravanan Indian Journal of Science and Technology 8 (13), 1, 2015 | 3 | 2015 |
A modified compression technique for trace data using dictionary method R Agalya, S Saravanan International Journal of Engineering and Technology 7 (2), 640-645, 2015 | 3 | 2015 |
Adapting scan based test vector for compression method based on transition technique S Saravanan, HN Upadhyay Procedia Engineering 30, 435-440, 2012 | 3 | 2012 |
Efficient Test Data Compression Achieved by Reduced Control Code S Saravanan, RV Sai, A Balasubramaniyan, R Silambamuthan, GD Babu, ... Procedia engineering 38, 680-684, 2012 | 3 | 2012 |
Improving the reliability of cache memories using identical tag bits SM Bharathi, RV Sai, S Saravanan Indian Journal of Science and Technology 9 (29), 1-5, 2016 | 2 | 2016 |
Cell stability and power reduction using dynamic isolated read static random access memory MS Vandhana, RV Sai, S Saravanan Indian Journal of Science and Technology 9 (29), 1-6, 2016 | 2 | 2016 |
Simultaneous signal selection for silicon debug through mixed-integer linear programming R Agalya, S Saravanan 2016 International Conference on Emerging Trends in Engineering, Technology …, 2016 | 2 | 2016 |
EFFICIENT MEMORY BUILT-IN SELF TEST FOR EMBEDDED SRAM USING PA ALGORITHM G PRAKASH, S SARAVANAN International Journal of Engineering and Technology 5 (2), 944-948, 2013 | 2 | 2013 |