Dr. Biju K Raveendran
Dr. Biju K Raveendran
Associate Professor, Dept. of Computer Science, BITS Pilani K K BIRLA Goa Campus
Verified email at goa.bits-pilani.ac.in - Homepage
Cited by
Cited by
Energy efficient real-time scheduling algorithm for mixed task set on multi-core processors
M Digalwar, P Gahukar, BK Raveendran, S Mohan
International Journal of Embedded Systems 9 (6), 523-534, 2017
A survey on replacement strategies in cache memory for embedded systems
P Panda, G Patil, B Raveendran
2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics …, 2016
Evaluation of priority based real time scheduling algorithms: choices and tradeoffs
BK Raveendran, S Balasubramaniam, S Gurunarayanan
Proceedings of the 2008 ACM symposium on Applied computing, 302-307, 2008
Stream: a simulation tool for energy efficient real time scheduling and analysis
M Digalwar, P Gahukar, S Mohan, BK Raveendran
Proceedings of 6th International Workshop on Analysis Tools and …, 2015
Predictive placement scheme in set-associative cache for energy efficient embedded systems
BK Raveendran, TSB Sudarshan, A Patil, K Randive, S Gurunarayanan
2008 International Conference on Signal Processing, Communications and …, 2008
Way halted prediction cache: An energy efficient cache architecture for embedded processors
NB Mallya, G Patil, B Raveendran
2015 28th International Conference on VLSI Design, 65-70, 2015
Variants of priority scheduling algorithms for reducing context-switches in real-time systems
BK Raveendran, KD Prasad, S Balasubramaniam, S Gurunarayanan
International Conference on Distributed Computing and Networking, 466-478, 2006
LAMCS: A leakage aware DVFS based mixed task set scheduler for multi-core processors
M Digalwar, BK Raveendran, S Mohan
Sustainable Computing: Informatics and Systems 15, 63-81, 2017
eduCloud: a VM communication aware, migration efficient cloud for scientific computing
BK Raveendran, P Joshi, S Mittal
International Journal of Communication Networks and Distributed Systems 18 …, 2017
Energy aware real time scheduling algorithm for mixed task set
M Digalwar, S Mohan, BK Raveendran
2013 International Conference on Advanced Electronic Systems (ICAES), 325-327, 2013
DPVFS: a dynamic procrastination cum DVFS scheduler for multi-core hard real-time systems
SK Gawali, BK Raveendran
International Journal of Embedded Systems 11 (4), 461-471, 2019
Simulation based performance study of cache coherence protocols
NB Mallya, G Patil, B Raveendran
2015 IEEE International Symposium on Nanoelectronic and Information Systems …, 2015
DPS: A dynamic procrastination scheduler for multi-core/multi-processor hard real time systems
SK Gawali, BK Raveendran
2016 International Conference on Control, Decision and Information …, 2016
Dynamicvoltage and frequency scaling scheduling algorithm for mixed task set
M Digalwar, S Mohan, BK Raveendran
2013 IEEE 8th International Conference on Industrial and Information Systems …, 2013
MEDIATOR-A Mixed Criticality Deadline Honored Arbiter for Multi-core Real-time Systems
AS Nair, LM Colaco, G Patil, BK Raveendran, S Punnekkatt
2019 IEEE/ACM 23rd International Symposium on Distributed Simulation and …, 2019
MOESIF: a MC/MP cache coherence protocol with improved bandwidth utilisation
NBMBKR Geeta Patil
Int. J. Embedded Systems 11 (4), 493 - 507, 2019
SMILEY: a mixed-criticality real-time task scheduler for multicore systems
A Sabu, B Raveendran, R Ghosh
2018 IEEE/ACM 22nd International Symposium on Distributed Simulation and …, 2018
LLRU: Late LRU Replacement Strategy for Power Efficient Embedded Cache
BK Raveendran, TSB Sudarshan, PD Kumar, P Tangudu, ...
15th International Conference on Advanced Computing and Communications …, 2007
Cache Memory Design with Late Replacements for Embedded Systems
SG B Raveendran, TSB Sudarshan
Int. Journal of Lateral Computing, 2006
LLFRP: An Energy Efficient Variant of LLF with Reduced Pre-emptions for Real–Time Systems
P Baid, S Prashanth, B Raveendran
GSTF Journal on Computing (JoC) 3 (4), 2014
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