| Design And Implementation Of Amba Apb Protocol J Mukunthan, AD Raj, S Keerthivadana, R Kiruthika, T Shruthi, S Snegasri IOP Conference Series: Materials Science and Engineering 1084 (1), 012050, 2021 | 3 | 2021 |
| FPGA implementation of ECC enabled multi-factor authentication (E-MFA) protocol for IoT based applications SR Sekar, S Elango, SP Philip, AD Raj Microelectronic Devices, Circuits and Systems: Second International …, 2021 | 3 | 2021 |
| Analysis of Voltage Transfer Characteristics of Nano-scale SOI CMOS Inverter with Variable Channel Length and Doping Concentration SD A.Daniyel Raj, C.Rajarajachozhan JOURNAL OF NANO- AND ELECTRONIC PHYSICS 7 (1), 01004-1 to 01004-4, 2015 | 2* | 2015 |
| Compensating Threshold Voltage Roll-Off in Nanoscale MOSFET with Parameter Adjustment SD C.Rajarajachozhan1 , A. Daniel Raj Journal of VLSI Design and Signal Processing 1 (2), 2015 | 2 | 2015 |
| INVESTIGATION AND VLSI IMPLEMENTATION OF LINEAR CONVOLUTION ARCHITECTURE FOR FPGA BASED SIGNAL PROCESSING APPLICATIONS ADR S Elango, P Sampath, K Shoukath Ali, Sajan P Philip International Journal of Pure and Applied Mathematics 119 (16), 4607-4624, 2018 | 1 | 2018 |
| Funds transfer authentication M Arif, S Philip, SR Donkada, R Ramanathan, J Iyer, ME Antony, ... US Patent App. 18/328,575, 2023 | | 2023 |
| Funds transfer authentication M Arif, S Philip, SR Donkada, R Ramanathan, J Iyer, ME Antony, ... US Patent 11,704,668, 2023 | | 2023 |
| Design of unsigned 2n+ 1 parallel residue arithmetic multiplier S Elango, P Sampath, SP Philip, AD Raj AIP Conference Proceedings 2725 (1), 2023 | | 2023 |
| Funds transfer authentication M Arif, S Philip, SR Donkada, R Ramanathan, J Iyer, ME Antony, ... US Patent 11,263,631, 2022 | | 2022 |
| Simulation and Performance Analysis of Different Adder Circuits Designed with DNA Logic Gates A Daniel Raj, VM Seeja, S Deb Journal of Nanoengineering and Nanomanufacturing 6 (2), 137-145, 2016 | | 2016 |
| DNA Logic Gates to Design a 4*4 bit Carry Select Adder Circuit ADR Seeja VM South Asian Journal of Engineering and Technology 2 (10), 1-6, 2016 | | 2016 |
| Wallace Tree Multiplier Design and Simulation with DNA Logic Gates SD A.Daniel Raj.Seeja V M Journal of VLSI Design and Signal Processing 2 (1), 1-16, 2016 | | 2016 |
| Efficient design of multiplier using GDI low power cell PS A.Daniel Raj, S.Vijayalakshmi International Journal of Computer Technology and Electronics Engineering 2 (6), 2012 | | 2012 |
ELANGO SBannari Amman Institute of Technology, SathyamangalamVerified email at bitsathy.ac.in
ELANGO SBannari Amman Institute of Technology, SathyamangalamVerified email at bitsathy.ac.in