| A security framework for noc using authenticated encryption and session keys HK Kapoor, GB Rao, S Arshi, G Trivedi Circuits, Systems, and Signal Processing 32, 2605-2622, 2013 | 59 | 2013 |
| Design of cryptographically secure AES like S‐Box using second‐order reversible cellular automata for wireless body area network applications BR Gangadari, S Rafi Ahamed Healthcare technology letters 3 (3), 177-183, 2016 | 42 | 2016 |
| Analysis and algebraic construction of S-Box for AES algorithm using irreducible polynomials BR Gangadari, SR Ahamed 2015 Eighth International Conference on Contemporary Computing (IC3), 526-530, 2015 | 14 | 2015 |
| FPGA implementation of compact S-box for AES algorithm using composite field arithmetic BR Gangadari, SR Ahamed 2015 Annual IEEE India Conference (INDICON), 1-5, 2015 | 12 | 2015 |
| Notice of Removal: Design of cryptographically secure AES S-Box using cellular automata BR Gangadari, SR Ahamed, R Mahapatra, RK Sinha 2015 International Conference on Electrical, Electronics, Signals …, 2015 | 10 | 2015 |
| Programmable cellular automata-based low-power architecture to S-box: An application to WBAN BR Gangadari, SR Ahamed Circuits, Systems, and Signal Processing 37 (3), 1116-1133, 2018 | 7 | 2018 |
| Low power VLSI architectures for cryptographic algorithms BR Gangadari Guwahati, 2018 | 2 | 2018 |
| FPGA implementation of hybrid linear cellular automata based encryption algorithm BR Gangadari, SR Ahamed 2017 International Conference on Communication and Signal Processing (ICCSP …, 2017 | 2 | 2017 |
| Low power S-box Architecture for AES algorithm using programmable second order reversible cellular automata: an application to WBAN BR Gangadari, SR Ahamed Journal of medical systems 40, 1-13, 2016 | 2 | 2016 |
| Low hardware complexity encryption algorithm using order 1-D programmable linear cellular automata BR Gangadari, SR Ahamed 2017 4th International Conference on Signal Processing and Integrated …, 2017 | | 2017 |
| 2017 4th International Conference on Signal Processing and Integrated Networks (SPIN) 2-3 February 2017, Noida, India A Roy, A Kumar, A Swarnkar, AK Verma, A Venkatesan, AG Mir, A Gupta, ... | | |
| Hardware Implementation of Fuzzy Logic Controller for DC-DC Buck Boost Converter using FPGA R Blange, BR Gangadari | | |
Hemangee K KapoorIndian Institute of Technology GuwahatiVerified email at iitg.ernet.in
