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Marif Daula Siddique
Marif Daula Siddique
Verified email at nus.edu.sg - Homepage
Title
Cited by
Cited by
Year
Optimal design of a new cascaded multilevel inverter topology with reduced switch count
MD Siddique, S Mekhilef, NM Shah, MA Memon
IEEE Access 7, 24498-24510, 2019
1502019
A new multilevel inverter topology with reduce switch count
MD Siddique, S Mekhilef, NM Shah, A Sarwar, A Iqbal, MA Memon
IEEE Access 7, 58584-58594, 2019
1172019
Low switching frequency based asymmetrical multilevel inverter topology with reduced switch count
MD Siddique, S Mekhilef, NM Shah, A Sarwar, A Iqbal, M Tayyab, ...
IEEE Access 7, 86374-86383, 2019
952019
A new switched capacitor 7L inverter with triple voltage gain and low voltage stress
MD Siddique, S Mekhilef, NM Shah, JSM Ali, F Blaabjerg
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (7), 1294-1298, 2019
772019
Single-phase step-up switched-capacitor-based multilevel inverter topology with SHEPWM
MD Siddique, S Mekhilef, S Padmanaban, MA Memon, C Kumar
IEEE Transactions on Industry Applications 57 (3), 3107-3119, 2020
492020
A single DC source nine-level switched-capacitor boost inverter topology with reduced switch count
MD Siddique, S Mekhilef, NM Shah, N Sandeep, JSM Ali, A Iqbal, ...
IEEE Access 8, 5840-5851, 2019
492019
A new single phase single switched-capacitor based nine-level boost inverter topology with reduced switch count and voltage stress
MD Siddique, S Mekhilef, NM Shah, JSM Ali, M Meraj, A Iqbal, ...
IEEE Access 7, 174178-174188, 2019
422019
A new single‐phase cascaded multilevel inverter topology with reduced number of switches and voltage stress
MD Siddique, S Mekhilef, NM Shah, A Sarwar, MA Memon
International Transactions on Electrical Energy Systems 30 (2), e12191, 2020
382020
Reduced switch count based single source 7L boost inverter topology
MD Siddique, JSM Ali, S Mekhilef, A Mustafa, N Sandeep, D Almakhles
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (12), 3252-3256, 2020
342020
Dual input switched‐capacitor‐based single‐phase hybrid boost multilevel inverter topology with reduced number of components
M Rawa, MD Siddique, S Mekhilef, N Mohamed Shah, H Bassi, ...
IET Power Electronics 13 (4), 881-891, 2020
332020
Asynchronous particle swarm optimization-genetic algorithm (APSO-GA) based selective harmonic elimination in a cascaded H-bridge multilevel inverter
MA Memon, MD Siddique, S Mekhilef, M Mubin
IEEE Transactions on Industrial Electronics 69 (2), 1477-1487, 2021
312021
Dual asymmetrical dc voltage source based switched capacitor boost multilevel inverter topology
MD Siddique, S Mekhilef, A Sarwar, A Alam, NM Shah
IET Power Electronics 13 (7), 1481-1486, 2020
292020
A New Configurable Topology for Multilevel Inverter With Reduced Switching Components.
MD Siddique, A Iqbal, MA Memon, S Mekhilef
IEEE Access 8, 188726-188741, 2020
272020
An improved asymmetrical multilevel inverter topology with reduced semiconductor device count
Z Sarwer, MD Siddique, A Iqbal, A Sarwar, S Mekhilef
International Transactions on Electrical Energy Systems 30 (11), e12587, 2020
242020
Extended multilevel inverter topology with reduced switch count and voltage stress
MD Siddique, S Mekhilef, M Rawa, A Wahyudie, B Chokaev, I Salamov
IEEE Access 8, 201835-201846, 2020
222020
A transformerless high gain dc–dc boost converter with reduced voltage stress
M Zaid, S Khan, MD Siddique, A Sarwar, J Ahmad, Z Sarwer, A Iqbal
International Transactions on Electrical Energy Systems 31 (5), e12877, 2021
172021
Single phase symmetrical and asymmetrical design of multilevel inverter topology with reduced number of switches
MD Siddique, A Mustafa, A Sarwar, S Mekhilef, NBM Shah, ...
2018 IEEMA Engineer Infinite Conference (eTechNxT), 1-6, 2018
172018
Recent trends and review on switched‐capacitor‐based single‐stage boost multilevel inverter
M Kumari, MD Siddique, A Sarwar, M Tariq, S Mekhilef, A Iqbal
International Transactions on Electrical Energy Systems 31 (3), e12730, 2021
152021
Reduced switch count-based N-level boost inverter topology for higher voltage gain
MD Siddique, BP Reddy, A Iqbal, S Mekhilef
IET Power Electronics 13 (15), 3505-3509, 2020
152020
7L-SCBI topology with minimal semiconductor device count
BP Reddy, MD Siddique, A Iqbal, S Mekhilef, S Rahman, PK Maroti
IET Power Electronics 13 (14), 3199-3203, 2020
152020
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