| An Efficient Optimization and Secured Triple Data Encryption Standard Using Enhanced Key Scheduling Algorithm A Vuppala, RS Roshan, S Nawaz, JVR Ravindra Elsevier, Procedia Computer Science 171, 1054-1063, 2020 | 30 | 2020 |
| Evaluation of deep learning models for detecting breast cancer using histopathological mammograms Images S Mohapatra, S Muduly, S Mohanty, JVR Ravindra, SN Mohanty Sustainable Operations and Computers 3, 296-302, 2022 | 24 | 2022 |
| Minimizing simultaneous switching noise (SSN) using modified odd/even bus invert method KS Sainarayanan, JVR Ravindra, MB Srinivas Third IEEE International Workshop on Electronic Design, Test and …, 2006 | 20 | 2006 |
| A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects KS Sainarayanan, JVR Ravindra, MB Srinivas 2006 IEEE International Symposium on Circuits and Systems (ISCAS), 4 pp.-4158, 2006 | 18 | 2006 |
| A Study on the Application of Machine Learning and Deep Learning Techniques for Skin Cancer Detection H Ghosh, IS Rahat, SN Mohanty, JVR Ravindra, A Sobur International Journal of Computer and Systems Engineering 18 (1), 51-59, 2024 | 15 | 2024 |
| Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach JVR Ravindra, SB Mandalika Proceedings of the 20th annual conference on Integrated circuits and systems …, 2007 | 13* | 2007 |
| Energy efficient spatial coding technique for low power VLSI applications JVR Ravindra, N Chittarvu, MB Srinivas 2006 6th International Workshop on System on Chip for Real Time Applications …, 2006 | 13 | 2006 |
| The enhancement of security measures in advanced encryption standard using double precision floating point multiplication model B Srikanth, MS Kumar, JVR Ravindra, KH Kishore Transactions on Emerging Telecommunications Technologies, e3948, 2020 | 11 | 2020 |
| Supervised machine learning for training a neural network as 5:2 compressor Maddisetti, L., Senapati, R.K., JVR Ravindra International Journal of Innovative Technology and Exploring Engineering 8 …, 2019 | 10 | 2019 |
| Power and area calibration of switch arbiter for high speed switch control and scheduling in network-on-chip S Singh, JVR Ravindra, BR Naik 2016 International SoC Design Conference (ISOCC), 5-6, 2016 | 10 | 2016 |
| A novel bus coding technique for low power data transmission JVR Ravindra, KS Sainarayanan, MB Srinivas IEEE symposium on VLSI design and test conference (VDAT-2005), 263-266, 2005 | 10 | 2005 |
| Accuracy evaluation of a trained neural network by energy efficient approximate 4: 2 compressor L Maddisetti, RK Senapati, JVR Ravindra Computers & Electrical Engineering 92, 107137, 2021 | 9 | 2021 |
| Machine learning based power efficient approximate 4: 2 compressors for imprecise multipliers L Maddisetti, JVR Ravindra 2019 32nd International Conference on VLSI Design and 2019 18th …, 2019 | 9 | 2019 |
| Training neural network as approximate 4:2 compressor applying machine learning algorithms for accuracy comparison M. Lavanya, RK Senapati, JVR Ravindra International Journal of Advanced Trends in Computer Science and Engineering …, 2019 | 9 | 2019 |
| CALPAN: Countermeasure against leakage power analysis attack by normalized DDPL C Padmini, JVR Ravindra 2016 International Conference on Circuit, Power and Computing Technologies …, 2016 | 9 | 2016 |
| A novel power-aware and high performance full adder cell for ultra-low power designs GR Ramireddy, JVR Ravindra 2014 International Conference on Circuits, Power and Computing Technologies …, 2014 | 8 | 2014 |
| A statistical model for estimating the effect of process variations on delay and slew metrics for VLSI interconnects JVR Ravindra, MB Srinivas 10th Euromicro Conference on Digital System Design Architectures, Methods …, 2007 | 8 | 2007 |
| Coupling aware energy-efficient data scrambling on memory-processor interfaces KS Sainarayanan, JVR Ravindra, C Raghunandan, MB Srinivas 2007 International Conference on Industrial and Information Systems, 421-426, 2007 | 8 | 2007 |
| Double precession floating point multiplier using schonhage – strassen algorithm used for FPGA accelerator B Srikanth, MS Kumar, JVR Ravindra, KH , Kishore International Journal of Emerging Trends in Engineering Research, 2019 | 7 | 2019 |
| Low-power near-explicit 5: 2 compressor for superior performance multipliers M Lavanya, RK Senapati, JVR Ravindra International Journal of Engineering 11 (4), 529-545, 2018 | 7 | 2018 |
Lavanya MaddisettiVardhaman College of EngineeringVerified email at vardhaman.org
