| Design and Analysis of Low-Power High-Speed Shared Charge Reset Technique based Dynamic Latch Comparator V Savani, NM Devashrayee Microelectronics Journal 74, 116 - 126, 2018 | 45 | 2018 |
| Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator V Savani, NM Devashrayee Analog Integrated Circuits and Signal Processing, 1-12, 2017 | 37 | 2017 |
| Design and implementation of low cost, portable telemedicine system: an embedded technology and ICT approach A Degada, V Savani 2015 5th Nirma University International Conference on Engineering (NUiCONE), 1-6, 2015 | 14 | 2015 |
| Analysis of power for double-tail current dynamic latch comparator V Savani, NM Devashrayee Analog Integrated Circuits and Signal Processing, 1-11, 2019 | 9 | 2019 |
| Analysis and Characterization of Various Current Mirror Topologies in 90 nm Technology J Chikani, P Chaudhari, V Savani International Journal of Emerging Technology and Advanced Engineering 2 (12 …, 2012 | 8 | 2012 |
| Implementation of Low Power Rail-To-Rail Dynamic Latch Comparator With Modified Adaptive Power Control Technique V Savani, NM Devashrayee Nirma University Journal of Engineering and Technology 5 (2), 1-7, 2017 | 7 | 2017 |
| Performance Analysis and Characterization of Shared Charge and Clocked-Latch based Comparator using 90-nm Technology V Savani, NM Devashrayee Journal of VLSI Design Tools & Technology 4 (3), 20-26, 2014 | 7 | 2014 |
| Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology V Savani, NM Devashrayee VLSI Design and Test (VDAT), 2015 19th International Symposium on, 1-2, 2015 | 6 | 2015 |
| Performance Analysis of PID Controller and Its significance for Closed Loop System A Patel, V Savani International Journal of Engineering Research & Technology (IJERT) 3 (3 …, 2014 | 6* | 2014 |
| Analysis and Characterization of Different Voltage Follower Topologies in 90 nm Technology J Aseem, J Padaliya, V Savani International Journal of Emerging Technology and Advanced Engineering 2 (12 …, 2012 | 6 | 2012 |
| Analysis And Characterization of Different Comparator Topologies A Kapadia, V Savani International Journal of Scientific & Technology Research 1 (11), 102-106, 2012 | 5 | 2012 |
| Dynamic Partial Reconfiguration of FPGA for SEU Mitigation and Area Efficiency V Savani, M Akash, G Nagendra International Journal of Advancements in Technology 2 (2), 285-291, 2011 | 5 | 2011 |
| Voice conversion algorithm M Akash, V Savani, S Rajvi, P Vaya Proceedings of the International Conference on Advances in Computing …, 2009 | 5* | 2009 |
| Implementation of Data Compression Algorithms on FPGA using Soft-core Processor V Savani, P Bhatasana, A Mecwan International Journal of Advancements in Technology 3 (4), 270-276, 2012 | 4 | 2012 |
| Development of SEU Monitor System for SEU Detection and Correction in virtex-5 FPGA V Savani, N Gajjar Engineering (NUiCONE), 2011 Nirma University International Conference on, 1-6, 2011 | 4 | 2011 |
| Performance analysis of Vedic mathematics algorithms on re-configurable hardware platform R Biji, V Savani Sādhanā 46 (2), 1-5, 2021 | 3 | 2021 |
| Design and Analysis of Source Current Effect on Preamplifier-Positive Feedback-based CMOS Comparator Using 90 nm Technology V Savani, NM Devashrayee Journal of VLSI Design Tools and Technology 3 (3), 16-26, 2013 | 3 | 2013 |
| A Low Power High Speed 15T FinFET-GDI Based Hybrid Full Adder Using 18 nm Technology P Bhau, V Savani Advances in VLSI, Communication, and Signal Processing, 445-456, 2022 | 2 | 2022 |
| Review of Adaptive Modulation Recognition Techniques V Savani, A Mecwan, P Bhatasana Journal of Communication Engineering & Systems 2 (2), 15. 32-41, 2012 | 2* | 2012 |
| Virtual makeover using mATLAB A Mecwan, V Savani Int. J. Advancements in Technology 1 (2), 2010 | 2 | 2010 |
Prof. (Dr.) Niranjan M DevashrayeeProfessor of Electronics & Communication EngineeringVerified email at nirmauni.ac.in
