Vijay Savani
Vijay Savani
Assistant Professor, EC, Institute of Technology, Nirma University
Verified email at nirmauni.ac.in - Homepage
Title
Cited by
Cited by
Year
Design and Analysis of Low-Power High-Speed Shared Charge Reset Technique based Dynamic Latch Comparator
V Savani, NM Devashrayee
Microelectronics Journal 74, 116 - 126, 2018
132018
Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator
V Savani, NM Devashrayee
Analog Integrated Circuits and Signal Processing, 1-12, 2017
72017
Design and implementation of low cost, portable telemedicine system: an embedded technology and ICT approach
A Degada, V Savani
2015 5th Nirma University International Conference on Engineering (NUiCONE), 1-6, 2015
72015
Analysis And Characterization of Different Comparator Topologies
A Kapadia, V Savani
International Journal of Scientific & Technology Research 1 (11), 102-106, 2012
52012
Analysis and Characterization of Various Current Mirror Topologies in 90 nm Technology
J Chikani, P Chaudhari, V Savani
International Journal of Emerging Technology and Advanced Engineering 2 (12á…, 2012
52012
Dynamic Partial Reconfiguration of FPGA for SEU Mitigation and Area Efficiency
V Savani, M Akash, G Nagendra
International Journal of Advancements in Technology 2 (2), 285-291, 2011
52011
Implementation of Low Power Rail-To-Rail Dynamic Latch Comparator With Modified Adaptive Power Control Technique
V Savani, NM Devashrayee
Nirma University Journal of Engineering and Technology 5 (2), 1-7, 2017
42017
Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology
V Savani, NM Devashrayee
VLSI Design and Test (VDAT), 2015 19th International Symposium on, 1-2, 2015
42015
Performance Analysis and Characterization of Shared Charge and Clocked-Latch based Comparator using 90-nm Technology
V Savani, NM Devashrayee
Journal of VLSI Design Tools & Technology 4 (3), 20-26, 2014
4*2014
Implementation of Data Compression Algorithms on FPGA using Soft-core Processor
V Savani, P Bhatasana, A Mecwan
International Journal of Advancements in Technology 3 (4), 270-276, 2012
32012
Analysis and Characterization of Different Voltage Follower Topologies in 90 nm Technology
J Aseem, J Padaliya, V Savani
International Journal of Emerging Technology and Advanced Engineering 2 (12á…, 2012
32012
Analysis of power for double-tail current dynamic latch comparator
V Savani, NM Devashrayee
Analog Integrated Circuits and Signal Processing, 1-11, 2019
22019
Design and Analysis of Source Current Effect on Preamplifier-Positive Feedback-based CMOS Comparator Using 90 nm Technology
V Savani, NM Devashrayee
Journal of VLSI Design Tools and Technology 3 (3), 16-26, 2013
2*2013
Development of SEU Monitor System for SEU Detection and Correction in virtex-5 FPGA
V Savani, N Gajjar
Engineering (NUiCONE), 2011 Nirma University International Conference on, 1-6, 2011
22011
Virtual makeover using mATLAB
A Mecwan, V Savani
Int. J. Advancements in Technology 1 (2), 2010
22010
Performance Analysis of PID Controller and Its significance for Closed Loop System
A Patel, V Savani
International Journal of Engineering Research & Technology (IJERT) 3 (3á…, 2014
12014
Voice conversion algorithm
M Akash, V Savani, S Rajvi, P Vaya
Proceedings of the International Conference on Advances in Computingá…, 2009
1*2009
Implementation of Sense Amplifier-Based D Flip-Flop using 0.25 Ám and 0.18 Ám Technology
P Bhatasana, V Savani, A Mecwan
Journal of Electronic Design Technology 4 (3), 10-13, 0
1*
Analysis and Design of Body Driven Dynamic Latch based Comparator in Low Supply Voltages with nMOS Driver
V Savani, NM Devashrayee
i-Manager's Journal on Electronics Engineering 7 (4), 1, 2017
2017
Design And Development of Auto Truck Loading System
AnkitSingh, V Savani, D Sharma
Journal on Embedded Systems 5 (3), 31-38, 2017
2017
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