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Dr. Kunal Sinha
Dr. Kunal Sinha
Asutosh College, University of Calcutta
Verified email at asutoshcollege.in
Title
Cited by
Cited by
Year
Study and analysis of the effects of SiGe source and pocket-doped channel on sensing performance of dielectrically modulated tunnel FET-based biosensors
S Kanungo, S Chattopadhyay, PS Gupta, K Sinha, H Rahaman
IEEE Transactions on Electron Devices 63 (6), 2589-2596, 2016
1112016
A device simulation-based investigation on dielectrically modulated fringing field-effect transistor for biosensing applications
S Kanungo, S Chattopadhyay, K Sinha, PS Gupta, H Rahaman
IEEE Sensors Journal 17 (5), 1399-1406, 2016
162016
A technique to incorporate both tensile and compressive channel stress in Ge FinFET architecture
K Sinha, S Chattopadhyay, PS Gupta, H Rahaman
Journal of Computational Electronics 16, 620-630, 2017
102017
An optoelectronic band-to-band tunnel transistor for near-infrared sensing applications: Device physics, modeling, and simulation
PS Gupta, H Rahaman, K Sinha, S Chattopadhyay
Journal of Applied Physics 120 (8), 084510, 2016
102016
An extremely low sub-threshold swing UTB SOI tunnel-FET structure suitable for low-power applications
PS Gupta, S Kanungo, H Rahaman, K Sinha, PS Dasgupta
International Journal of Applied Physics and Mathematics 2 (4), 240, 2012
92012
Surface engineering of solar glass covers for soiling related issues by applying electrodynamic screens (EDS)
RB Shoubhik De, Manish Kumar, Silajit Manna, Sugato Ghosh, Kunal Sinha ...
Surfaces and Interfaces 25, 101222, 2021
62021
Investigation of Process Induced Stress in the Channel of a SiGe Embedded Source/Drain Ge- FinFET Architecture
K Sinha, S Chattopadhyay, H Rahaman
International Symposium on Devices, Circuits and Systems, 2018
32018
A study on the performance of stress induced p-channel MOSFETs with embeded Si1−xGexsource/drain
K Sinha, H Rahaman, S Chattopadhyay
2012 5th International Conference on Computers and Devices for Communication …, 2012
32012
Incorporation of Tensile and Compressive channel Stress by Modulating SiGe Stressor length in Embedded Source/Drain Si-FinFET Architecture
K Sinha, PS Gupta, C Sanatan, H Rahaman
2018 IEEE Electron Device Kolkata Conference, 2018
22018
Investigation of the Impact of Embedded SiGe Source/Drain Induced Uniaxial Stress on the Performance of Si p-channel 3D FinFETs
K Sinha, H Rahaman, S Chattopadhyay
6th International Conference on Computers and Devices for Comminication …, 2015
22015
Strain engineering in modern field effect transistors
K Sinha
Electrical and Electronic Devices, Circuits, and Materials: Technological …, 2021
12021
Investigating the performance of SiGe embedded dual source p-FinFET architecture
K Sinha, PS Gupta, S Chattopadhyay, H Rahaman
Superlattices and Microstructures 98, 37-45, 2016
12016
Three Dimensional Process Induced Stress in Nano-scale MOSFET using Embedded Source/Drain Technology
K Sinha
International Conference on Advanced Materials and Energy Technology (ICAMET …, 2014
12014
Evolution of Nanoscale Transistors: From Planner MOSFET to 2D-Material-Based Field-Effect Transistors
K Sinha
Nanotechnology, 119-135, 2022
2022
Performance-Aware Stress Engineering in Nano-scaled FETs with Embedded SiGe Source and Drain
K Sinha
Lap-Lambert Academic Publishing, 2019
2019
Method to Analyze Channel Stress in Ge FinFET Architecture and architecture thereof
K Sinha, PS Gupta, C Sanatan, H Rahaman
IN Patent App. 201,831,020,551, 2018
2018
A Study on the Performance of Strained Channel Dual Source Field Effect Transistor for Bio-Sensing Application
K Sinha, S Chattopadhyay, H Rahaman
Two Days National Conference on Advances in Interdisciplinary Sciences, 2017
2017
STRAINED SILICON – A GATEWAY TO A FASTER WORLD
K Sinha, H Rahaman, S Chattopadhyay
National Conference on Advancement in Frontier Physics: From 20th century to …, 2016
2016
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