| Low-power hybrid 1-bit full-adder circuit for energy efficient arithmetic applications MC Parameshwara, HC Srinivasaiah Journal of Circuits, Systems and Computers 26 (01), 1750014, 2017 | 44 | 2017 |
| Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations HC Srinivasaiah, N Bhat IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003 | 15 | 2003 |
| Low power and area efficient FFT architecture through decomposition technique HC Srinivasaiah, KS Shashidhara 2017 International Conference on Computer Communication and Informatics …, 2017 | 11 | 2017 |
| Optimization of 0.1 μm NMOS transistor using disposable spacer technique HC Srinivasaiah, N Bhat Proceedings of VLSI Design and Test Workshop, 298-303, 2001 | 11 | 2001 |
| Characterization of sub-100 nm CMOS process using screening experiment technique HC Srinivasaiah, N Bhat Solid-state electronics 49 (3), 431-436, 2005 | 10 | 2005 |
| Response surface modeling of 100nm cmos process technology using design of experiment HC Srinivasaiah, N Bhat VLSI Design, International Conference on, 285-285, 2004 | 9 | 2004 |
| Implications of halo implant shadowing and backscattering from mask layer edges on device leakage current in 65nm SRAM HC Srinivasaiah 2012 25th International Conference on VLSI Design, 412-417, 2012 | 5 | 2012 |
| Monte Carlo analysis of the implant dose sensitivity in 0.1 μm NMOSFET HC Srinivasaiah, N Bhat Solid-State Electronics 47 (8), 1379-1383, 2003 | 5 | 2003 |
| Statistical Modeling of Transistor Mismatch Effects in 100nm CMOS devices HC Srinivasaiah | 3 | 2011 |
| Implant dose sensitivity of 0.1/spl mu/m CMOS inverter delay HC Srinivasaiah, N Bhat Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design …, 2002 | 3 | 2002 |
| Study of spectral purity dependence on sine-ROM size in a digitally controlled frequency synthesizer MC Parameshwara, HC Srinivasaiah 2017 International Conference on Wireless Communications, Signal Processing …, 2017 | 2 | 2017 |
| Overview of airborne SAR data processing alogorithms V Joshi, S Manikandan, HC Srinivasaiah 2017 International Conference on Innovative Mechanisms for Industry …, 2017 | 2 | 2017 |
| A Novel Low Power 1-bit Full Adder with CMOS Transmission-gate Architecture for Portable Application MC Parameshwara, KS Shashidhara, S HC Proc. of Emerging Research in Computing, Information, Communication and …, 2013 | 2 | 2013 |
| A Mathematical Attack Based Algorithm to Challenge the Security of RSA Cryptosystem NR Mise, HC Srinivasaiah Int. J. Adv. Res. Technol 2 (6), 202-205, 2013 | 2 | 2013 |
| Location estimation of beacon in MEOSAR system CH Sowmya, HC Srinivasaiah Int. J. Electron. Signals. Syst 1 (2), 69-75, 2012 | 2 | 2012 |
| Choice of Adders for Multimedia Processing Applications: Comparison of Various Existing and a Novel 1-Bit Full Adder MC Parameshwara, HC Srinivasaiah IOSR Journal of Electronics and Communication Engineering, e-ISSN, 2278-2834, 0 | 2 | |
| Hardware co-simulation of 1024-point FFT and it's Implementation, in Simulink, Xilinx Vivado IDE on Zynq-7000 FPGA KS Shashidhara, HC Srinivasaiah European Journal of Engineering and Technology Research 4 (9), 58-64, 2019 | 1 | 2019 |
| Partial Product Compression Methods: A Study and Performance Comparison Using a Tree Structured Multipliers MC Parameshwara, HC Srinivasaiah International Journal of Engineering Research and General Science 4 (2), 749-756, 2016 | 1 | 2016 |
| Study of power-delay characteristics of a mixed-Logic-Style Novel Adder Circuit at 90nm Gate Length MC Parameshwara, HC Srinivasaiah International Journal of Computer Applications 119 (4), 2015 | 1 | 2015 |
| Implementation of 1024-point FFT Soft-Core to Characterize Power and Resource Parameters in Artix-7, Kintex-7, Virtex-7, and Zynq-7000 FPGAs KS Shashidhara, HC Srinivasaiah European Journal of Engineering and Technology Research 4 (9), 81-88, 2019 | | 2019 |
