Harish Ram D S
Harish Ram D S
Assistant Professor (ECE), Amrita Vishwa Vidyapeetham University
Verified email at cb.amrita.edu
TitleCited byYear
A novel framework for applying multiobjective GA and PSO based approaches for simultaneous area, delay, and power optimization in high level synthesis of datapaths
DS Ram, MC Bhuvaneswari, SS Prabhu
VLSI design 2012, 2, 2012
282012
A novel evolutionary technique for multi-objective power, area and delay optimization in high level synthesis of datapaths
DSH Ram, MC Bhuvaneswari, SM Logesh
2011 IEEE Computer Society Annual Symposium on VLSI, 290-295, 2011
182011
A survey of High-Level Synthesis techniques for area, delay and power optimization
SM Logesh, DS Ram, MC Bhuvaneswari
International Journal of Computer Applications 32 (10), 3935-3952, 2011
82011
Modeling of consumption data for forecasting in automated metering infrastructure (AMI) systems
AJ Balaji, DSH Ram, BB Nair
Computer Science On-line Conference, 165-173, 2016
52016
Multi-objective optimization of power, area and delay during high-level synthesis of DFG's—A genetic algorithm approach
SM Logesh, DSH Ram, MC Bhuvaneswari
2011 3rd International Conference on Electronics Computer Technology 1, 108-112, 2011
52011
Machine learning approaches to electricity consumption forecasting in automated metering infrastructure (ami) systems: An empirical study
AJ Balaji, DSH Ram, BB Nair
Computer Science On-line Conference, 254-263, 2017
32017
Hardware implementation of quasigroup based encryption
NA Nikhil, DSH Ram
2014 International Conference on Embedded Systems (ICES), 55-58, 2014
32014
Improved low power FPGA binding of datapaths from data flow graphs with NSGA II-based schedule selection
DSH Ram, MC Bhuvaneswari, S Umadevi
Advances in Electrical and Computer Engineering 13 (4), 85-93, 2013
32013
FPGA BASED SYSTEM FOR DENIAL OF SERVICE DETECTION IN SMART GRID
AJ Balaji, DSH Ram
22015
Applicability of deep learning models for stock price forecasting an empirical study on Bankex data
AJ Balaji, DSH Ram, BB Nair
Procedia computer science 143, 947-953, 2018
12018
Design space exploration for scheduling and allocation in high level synthesis of Datapaths
MC Bhuvaneswari, DSH Ram, R Neelaveni
Application of Evolutionary Algorithms for Multi-objective Optimization in …, 2015
12015
High level synthesis of data flow graphs using integer linear programming for switching power reduction
SA Yazhini, DSH Ram
2011 International Conference on Signal Processing, Communication, Computing …, 2011
12011
FPGA Implementation of Face Recognition using Eigen Values
RR Menon, M Verma, S Harikrishnan, KV Suraj, S Adarsh, DSH Ram
Conference Proceedings RTCSP 9, 177, 0
nids
dhanesh
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Articles 1–14