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Sriseshan Srikanth
Sriseshan Srikanth
Memory System Architect at Reality Labs, Meta
Verified email at fb.com
Title
Cited by
Cited by
Year
Extending Moore’s law via computationally error-tolerant computing
B Deng, S Srikanth, ER Hein, TM Conte, E Debenedictis, J Cook, ...
ACM Transactions on Architecture and Code Optimization (TACO) 15 (1), 1-27, 2018
122018
The superstrider architecture: Integrating logic and memory towards non-von neumann computing
S Srikanth, TM Conte, EP DeBenedictis, J Cook
2017 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2017
122017
Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C
EP DeBenedictis, J Cook, S Srikanth, TM Conte
2017 IEEE High Performance Extreme Computing Conference (HPEC), 1-7, 2017
112017
Computationally-redundant energy-efficient processing for y'all (CREEPY)
B Deng, S Srikanth, ER Hein, PG Rabbat, TM Conte, E DeBenedictis, ...
2016 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2016
112016
MetaStrider: Architectures for scalable memory-centric reduction of sparse data streams
S Srikanth, A Jain, JM Lennon, TM Conte, E Debenedictis, J Cook
ACM Transactions on Architecture and Code Optimization (TACO) 16 (4), 1-26, 2019
102019
Tackling memory access latency through dram row management
S Srikanth, L Subramanian, S Subramoney, TM Conte, H Wang
Proceedings of the International Symposium on Memory Systems, 137-147, 2018
82018
Experimental insights from the rogues gallery
JS Young, J Riedy, TM Conte, V Sarkar, P Chatarasi, S Srikanth
2019 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2019
72019
Memory system design for ultra low power, computationally error resilient processor microarchitectures
S Srikanth, PG Rabbat, ER Hein, B Deng, TM Conte, E DeBenedictis, ...
2018 IEEE International Symposium on High Performance Computer Architecture …, 2018
72018
Merge network for a non-von Neumann accumulate accelerator in a 3D chip
A Jain, S Srikanth, EP DeBenedictis, T Krishna
2018 IEEE International Conference on Rebooting Computing (ICRC), 1-11, 2018
52018
Energy efficiency limits of logic and memory
S Agarwal, J Cook, E DeBenedictis, MP Frank, G Cauwenberghs, ...
2016 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2016
52016
Intrepydd: performance, productivity, and portability for data science application kernels
T Zhou, J Shirako, A Jain, S Srikanth, TM Conte, R Vuduc, V Sarkar
Proceedings of the 2020 ACM SIGPLAN International Symposium on New Ideas …, 2020
42020
Scoreboard approach to managing idle page close timeout duration in memory
S Srikanth, L Subramanian, S Subramoney
US Patent 10,176,124, 2019
32019
A brief survey of non-residue based computational error correction
S Srikanth, B Deng, TM Conte
arXiv preprint arXiv:1611.03099, 2016
32016
Scalable Energy-Efficient Microarchitectures with Computational Error Tolerance via Redundant Residue Number Systems
B Deng, S Srikanth, A Jain, TM Conte, E DeBenedictis, J Cook
IEEE Transactions on Computers 71 (3), 613-627, 2021
22021
Systems and methods for page management using local page information
S Srikanth, L Subramanian, S Subramoney
US Patent 10,191,689, 2019
22019
SortCache: intelligent cache management for accelerating sparse data workloads
S Srikanth, A Jain, TM Conte, EP Debenedictis, J Cook
ACM Transactions on Architecture and Code Optimization (TACO) 18 (4), 1-24, 2021
12021
Energy efficient architectures for irregular data streams
S Srikanth
Georgia Institute of Technology, 2020
2020
Superstrider: Implications of 3D Chips to GraphChallenge.
E Debenedictis, S Srikanth, J Cook, TM Conte
Sandia National Lab.(SNL-NM), Albuquerque, NM (United States), 2017
2017
Superstrider Sparse-to-Dense Stream Converter (Simulation).
S Srikanth, E Debenedictis, J Cook, TM Conte
Sandia National Lab.(SNL-NM), Albuquerque, NM (United States), 2017
2017
Superstrider and the 3rd Path Beyond Moore? s Law.
E Debenedictis, J Cook, S Srikanth, TM Conte
Sandia National Lab.(SNL-NM), Albuquerque, NM (United States), 2017
2017
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