| Subthreshold Analog/RF Performance Enhancement of Underlap DG FETs With High- k Spacer for Low Power Applications K Koley, A Dutta, B Syamal, SK Saha, CK Sarkar IEEE Transactions on Electron Devices 60 (1), 63 - 69, 2013 | 67 | 2013 |
| Analysis of High-κ Spacer Asymmetric Underlap DG-MOSFET for SOC Application K Koley, A Dutta, SK Saha, CK Sarkar IEEE Transactions on Electron Devices 62 (6), 1733 - 1738, 2015 | 45 | 2015 |
| Impact of the lateral straggle on the Analog and RF performance of TFET S Ghosh, K Koley, CK Sarkar Microelectronics Reliability 55 (2), 326-331, 2014 | 45 | 2014 |
| Subthreshold analog/RF performance of underlap DG FETs with asymmetric source/drain extensions K Koley, B Syamal, A Kundu, N Mohankumar, CK Sarkar Microelectronics Reliability 52 (11), 2572-2578, 2012 | 34 | 2012 |
| Deep insight into linearity and NQS parameters of tunnel FET with emphasis on lateral straggle S Ghosh, K Koley, CK Sarkar Micro & Nano Letters 13 (1), 35-40, 2018 | 27 | 2018 |
| Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET A Kundu, K Koley, A Dutta, CK Sarkar Microelectronics Reliability 54 (12), 2717-2722, 2014 | 27 | 2014 |
| Study of body and oxide thickness variation on analog and RF performance of underlap DG-MOSFETs SK Pati, K Koley, A Dutta, N Mohankumar, CK Sarkar Microelectronics Reliability 54 (6-7), 1137-1142, 2014 | 25 | 2014 |
| Effect of Source/Drain Lateral Straggle on Distortion and Intrinsic Performance of Asymmetric Underlap DG-MOSFETs K Koley, A Dutta, SK Saha, CK Sarkar IEEE Journal of the Electron Devices Society 2 (6), 135-144, 2014 | 22 | 2014 |
| A subthreshold surface potential modeling of drain/source edge effect on double gate MOS transistor S Namana, S Baishya, K Koley 2010 International Conference on Electronics and Information Engineering 1 …, 2010 | 15 | 2010 |
| Analysis of Harmonic Distortion in UDG-MOSFETs A Dutta, K Koley, SK Saha, CK Sarkar IEEE Transactions on Electron Devices 61 (4), 998-1005, 2014 | 14 | 2014 |
| High Performance Asymmetric Underlap Ge-pTFET with Pocket Implantation S Ghosh, K Koley, SK Saha, CK Sarkar IEEE Transactions on Electron Devices 63 (10), 3869 - 3875, 2016 | 10 | 2016 |
| Physical Insights Into Electric Field Modulation in Dual-k Spacer Asymmetric Underlap FinFET A Dutta, K Koley, SK Saha, CK Sarkar IEEE Transactions on Electron Devices 63 (8), 3019 - 3027, 2016 | 10 | 2016 |
| Impact of temperature on linearity and harmonic distortion characteristics of underlapped FinFET A Dutta, K Koley, SK Saha, CK Sarkar Microelectronics Reliability 61, 99-105, 2016 | 10 | 2016 |
| The Understanding of SiNR and GNR TFETs for Analog and RF Application With Variation of Drain-Doping Molar Fraction BC Mech, K Koley, J Kumar IEEE Transactions on Electron Devices 65 (10), 4694 - 4700, 2018 | 9 | 2018 |
| Analysis of Harmonic distortion in asymmetric underlap DG-MOSFET with high-k spacer A Dutta, K Koley, CK Sarkar Microelectronics Reliability 54 (6-7), 1125-1132, 2014 | 9 | 2014 |
| Impact of underlap and mole-fraction on RF performance of strained-Si/Si1− xGex/strained-Si DG MOSFETs A Dutta, K Koley, CK Sarkar Superlattices and Microstructures 75, 634-646, 2014 | 8 | 2014 |
| RF parameter extraction of Bulk FinFET: A non quasi static approach A Kundu, B Syamal, K Koley, CK Sarkar, N Mohankumar 2010 IEEE International Conference of Electron Devices and Solid-State …, 2010 | 8 | 2010 |
| Study of circuit performance and non quasi static effect in germanium tunnel FET for different temperatures S Ghosh, K Koley, CK Sarkar Microelectronics Journal 90, 204-210, 2019 | 7 | 2019 |
| An Analytical BTBT Current Model of Symmetric/Asymmetric 4T Tunnel Double Gate FETs With Ambipolar Characteristic P Dutta, K Koley, A Dutta, CK Sarkar IEEE Transactions on Electron Devices 63 (7), 2700 - 2707, 2016 | 7 | 2016 |
| Design and study of programmable ring oscillator using IDUDGMOSFET S Mukherjee, S Roy, K Koley, A Dutta, CK Sarkar Solid-State Electronics 117, 193-198, 2016 | 7 | 2016 |
