Low-temperature tunneling spectroscopy of Ge (111) c (2× 8) surfaces RM Feenstra, S Gaan, G Meyer, KH Rieder Physical Review B 71 (12), 125316, 2005 | 89 | 2005 |
Size, shape, composition, and electronic properties of InAs/GaAs quantum dots by scanning tunneling microscopy and spectroscopy S Gaan, G He, RM Feenstra, J Walker, E Towe Journal of Applied Physics 108 (11), 2010 | 44 | 2010 |
Shallow trench isolation integration methods and devices formed thereby H Shen, K Na, S Gaan, HN Tai, W Tong, SC Han, TH Kim, JH Han, ... US Patent 9,123,771, 2015 | 38 | 2015 |
Structure and electronic spectroscopy of steps on GaAs (110) surfaces S Gaan, RM Feenstra, P Ebert, RE Dunin-Borkowski, J Walker, E Towe Surface science 606 (1-2), 28-33, 2012 | 27 | 2012 |
Electronic states of InAs/GaAs quantum dots by scanning tunneling spectroscopy S Gaan, G He, RM Feenstra, J Walker, E Towe Applied Physics Letters 97 (12), 2010 | 18 | 2010 |
Methods for fabricating integrated circuits using flowable chemical vapor deposition techniques with low-temperature thermal annealing X Dou, S Hong, S Shinde, S Gaan, T Han, C Chacon, S Yamaguchi US Patent 9,831,098, 2017 | 15 | 2017 |
PMD and STI gap-fill challenges for advanced technology of logic and eNVM H Liu, S Srivathanakul, HW Liu, S Gaan, X Cai, X Rao, J Shu, S Kim ECS Transactions 52 (1), 397, 2013 | 12 | 2013 |
Patterning multiple, dense features in a semiconductor device using a memorization layer G Bouche, ACH Wei, X Hu, JF Wandell, S Gaan US Patent 9,224,842, 2015 | 9 | 2015 |
A comparison of various surface finishes and the effects on the early stages of pore formation during high field etching of SiC Y Ke, C Moisson, S Gaan, RM Feenstra, RP Devaty, WJ Choyke Materials science forum 527, 743-746, 2006 | 8 | 2006 |
Processes for preparing integrated circuits with improved source/drain contact structures and integrated circuits prepared according to such processes S Gaan, S Gu US Patent 9,466,701, 2016 | 7 | 2016 |
Methods for fabricating integrated circuits utilizing silicon nitride layers H Cao, H Liu, HS Wong, S Srivathanakul, S Gaan US Patent 8,940,650, 2015 | 5 | 2015 |
Method for forming a shallow trench isolation structure using a nitride liner and a diffusionless anneal S Gaan, S Ray, V Chauhan US Patent App. 15/225,994, 2018 | 4 | 2018 |
Quantitative determination of nanoscale electronic properties of semiconductor surfaces by scanning tunnelling spectroscopy RM Feenstra, S Gaan Journal of Physics: Conference Series 326 (1), 012009, 2011 | 4 | 2011 |
FinFET devices comprising a dielectric layer/CMP stop layer/hardmask/etch stop layer/gap-fill material stack G Bouche, A Wei, X Hu, JF Wandell, S Gaan US Patent 9,520,395, 2016 | 3 | 2016 |
Shallow trench isolation integration methods and devices formed thereby H Shen, K Na, S Gaan, HN Tai, W Tong, SC Han, TH Kim, JH Han, ... US Patent 9,385,192, 2016 | 2 | 2016 |
Method of fabricating an interlayer structure of increased elasticity modulus S Ray, S Gaan, JP Liu, Z Sun US Patent 9,076,645, 2015 | 2 | 2015 |
Part 1-Chapter 4-Porous SiC, SiC Nanoparticles and Nanowires-A Comparison of Various Surface Finishes and the Effects on the Early Stages of Pore Formation during High Field … YMC Ke, SFRM Gaan, RPCWJ Devaty Materials Science Forum 527529, 743-746, 2006 | 1 | 2006 |
Devices comprising high-K dielectric layer and methods of forming same S Ray, Y Liu, JP Liu, F D'addamio, S Gaan US Patent 9,673,039, 2017 | | 2017 |
Semiconductor substrates and methods for processing semiconductor substrates S Ray, S Gaan, S Meyers, N Pillai, EK Banghart, K Jung US Patent 9,570,291, 2017 | | 2017 |
Inhibiting diffusion of elements between material layers of a layered circuit structure S Gu, S Gaan, Z Sun, H Liu, A Selsley US Patent 9,502,232, 2016 | | 2016 |