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Mamidala Jagadesh Kumar.
Mamidala Jagadesh Kumar.
Verified email at ee.iitd.ac.in - Homepage
Title
Cited by
Cited by
Year
Doping-less tunnel field effect transistor: Design and investigation
MJ Kumar, S Janardhanan
IEEE transactions on Electron Devices 60 (10), 3285-3290, 2013
5962013
Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review
A Chaudhry, MJ Kumar
IEEE Transactions on Device and Materials Reliability 4 (1), 99-109, 2004
5162004
Novel attributes of a dual material gate nanoscale tunnel field-effect transistor
S Saurabh, MJ Kumar
IEEE transactions on Electron Devices 58 (2), 404-410, 2010
4642010
Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs
MJ Kumar, A Chaudhry
IEEE Transactions on Electron Devices 51 (4), 569-574, 2004
3342004
Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain
DB Abdi, MJ Kumar
IEEE Journal of the Electron Devices Society 2 (6), 187-190, 2014
3042014
A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation
GV Reddy, MJ Kumar
IEEE Transactions on Nanotechnology 4 (2), 260-268, 2005
2892005
Bipolar charge-plasma transistor: a novel three terminal device
MJ Kumar, K Nadda
IEEE Transactions on Electron Devices 59 (4), 962-967, 2012
2162012
Fundamentals of tunnel field-effect transistors
S Saurabh, MJ Kumar
CRC press, 2016
1932016
Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET
A Chaudhry, MJ Kumar
IEEE Transactions on Electron Devices 51 (9), 1463-1467, 2004
1612004
Impact of strain on drain current and threshold voltage of nanoscale double gate tunnel field effect transistor: Theoretical investigation and analysis
S Saurabh, MJ Kumar
Japanese Journal of Applied Physics 48 (6R), 064503, 2009
1582009
In-Built N+Pocket p-n-p-n Tunnel Field-Effect Transistor
DB Abdi, MJ Kumar
IEEE Electron Device Letters 35 (12), 1170-1172, 2014
1542014
Tunnel field-effect transistors (TFET)
JK Mamidala, R Vishnoi, P Pandey
John Wiley and Sons Ltd., West Sussex, UK, 2016
148*2016
Controlling the drain side tunneling width to reduce ambipolar current in tunnel FETs using heterodielectric BOX
S Sahay, MJ Kumar
IEEE transactions on electron devices 62 (11), 3882-3886, 2015
1292015
Dielectric-modulated impact-ionization MOS transistor as a label-free biosensor
N Kannan, MJ Kumar
IEEE electron device letters 34 (12), 1575-1577, 2013
1242013
Compact analytical model of dual material gate tunneling field-effect transistor using interband tunneling and channel transport
R Vishnoi, MJ Kumar
IEEE Transactions on Electron Devices 61 (6), 1936-1942, 2014
1172014
Nanotube junctionless FET: proposal, design, and investigation
S Sahay, MJ Kumar
IEEE Transactions on Electron Devices 64 (4), 1851-1856, 2017
1062017
New dual-material SG nanoscale MOSFET: analytical threshold-voltage model
MJ Kumar, AA Orouji, H Dhakad
IEEE transactions on Electron Devices 53 (4), 920-922, 2006
1022006
Compact analytical drain current model of gate-all-around nanowire tunneling FET
R Vishnoi, MJ Kumar
IEEE Transactions on Electron Devices 61 (7), 2599-2603, 2014
992014
Insight into lateral band-to-band-tunneling in nanowire junctionless FETs
S Sahay, MJ Kumar
IEEE Transactions on Electron Devices 63 (10), 4138-4142, 2016
972016
Junctionless field-effect transistors: design, modeling, and simulation
S Sahay, MJ Kumar
John Wiley & Sons, 2019
932019
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